KSZ9563RNXI datasheet(49/226 Pages) MICROCHIP

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DS00002419D-page 49

KSZ9563R

The RMII interface uses a single 50MHz clock. This REFCLK may be sourced either from the KSZ9563R or from the

connected device. A strapping option is used to select the mode. “Normal Mode” is the mode where the other device

supplies the clock, and the clock is an input to the REFCLKI pin of the device. “Clock Mode” is the mode where the

KSZ9563R generates the 50MHz clock on the REFCLKO pin.

The RGMII interface employs source synchronous clocking, so it is symmetrical and does not require a mode selection.

An output clock is generated on the RX_CLK pin, while an input clock is received on the TX_CLK pin. The clock speed

scales with the interface data rate - either 10, 100 or 1000 Mbps. A strapping option is used to select between the 100

and 1000 Mbps speeds. If the 10 Mbps rate is required, then a register setting is used to set that speed.

The MAC interfaces are powered from VDDIO.

4.6.3

SERIAL MANAGEMENT INTERFACE CLOCK

Whether configured to be SPI, I2C or MIIM, the KSZ9563R is always a slave and receives the clock as an input. The

serial management interface is powered from VDDIO.

4.7

Power

The KSZ9563R requires two to three supply voltages. The device core operates from a 1.2V supply (DVDDL and

AVDDL). The PHY transceivers and XI/XO crystal/clock interface operate from a 2.5V or 3.3V supply (AVDDH). The

digital I/O's can be operated from 1.8V, 2.5V or 3.3V (VDDIO). The digital I/Os powered from VDDIO include RGMII,

RMII, MII, SPI, I2C, MIIM, LED, RESET_N, PME_N, and INTRP_N.

4.8

Power Management

The device supports enhanced power management features in a low-power state with energy detection to ensure low-

power dissipation during device idle periods. There are three operation modes under the power management function

which are implemented globally (i.e., applying to all ports):

• Normal Operation Mode

• Energy Detect Mode

• Global Soft Power Down Mode

Table 4-23 summarizes all internal function blocks status under the four power-management operation modes.

There are two additional power saving modes that may be implemented on a per-port basis:

• Port-Based Power Down

• Energy Efficient Ethernet (EEE) - Active only if enabled in the device and auto-negotiated (per-port) with a link

partner. EEE can be enabled on a per-port basis for the PHY ports only.

The first four global power modes are mutually exclusive; only one mode may be selected at a time. The per-port power

modes may be enabled independent of one another, and independent of the global power mode.

Note:

Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information on using configuration

straps.

TABLE 4-23:

MDI/MDI-X PIN DEFINITIONS

Functional Blocks

Power Management Operation Modes

Normal Mode

Energy Detect Mode

Soft Power Down Mode

Internal PLL Clock

Enabled

Disabled

TX/RX PHYs

Enabled

Energy Detect at RX

Disabled

MACs

Enabled

Disabled

Host Interface

Enabled

Disabled

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