KSZ9563RNXI datasheet(59/226 Pages) MICROCHIP

59 / 226 page

 2017-2018 Microchip Technology Inc.

DS00002419D-page 59

KSZ9563R

While in RMII Normal Mode, the port will require an external 50MHz signal to be input to TX_CLK/REFCLKI from an

external source. This mode is selected by strapping the LED2_0 pin high during reset.

While in RMII Clock Mode, the port will output a 50MHz clock on RX_CLK/REFCLKO, which is derived from the 25MHz

crystal or oscillator attached to the XI clock input. The TX_CLK/REFCLKI input is unused in this mode. This mode is

selected by strapping the LED2_0 pin low during reset.

Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional configuration strap information.

Table 4-29 describes the signals used by the RMII interface. Refer to the RMII specification for full details on the signal

descriptions.

Port 3 in RMII mode may connect to either an external MAC device (such as a host processor) or to an external PHY;

but unlike MII, RMII does not provide separate PHY and MAC modes of operation. However, it is necessary to connect

the pins properly.

TABLE 4-29:

RMII SIGNAL DESCRIPTIONS

RMII Signal

Name

(per spec)

RMII Signal

(per KSZ9563R)

Pin Direction

(with respect to

PHY, KSZ9563R)

Pin Direction

(with respect to

MAC)

RMII Signal Description

REF_CLK

REFCLKI

Input

Input or Output

Synchronous 50MHz reference clock,

when port is in RMII Normal Mode

n/a

REFCLKO

Output

Input

Synchronous 50MHz reference clock,

when port is in RMII Clock Mode

TX_EN

Input

Output

Transmit Enable

TXD[1:0]

Input

Output

Transmit Data Bit [1:0]

CRS_DV

Output

Input

Carrier Sense / Receive Data Valid

RX_ER

Output

Input or

not required

Receive Error

RXD[1:0]

Output

Input

Receive Data Bit [1:0]

TABLE 4-30:

RMII CONNECTION TO EXTERNAL MAC

RMII Interface Signals Description

KSZ9563R Signals

External MAC Device Signals

Transmit Enable

TX_EN (input)

TX_EN (output)

Transmit Data Bits [1:0]

TXD[1:0] (input)

TXD[1:0] (output)

Reference Clock

REFCLKI (input)

or REFCLKO (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

CRS_DV (output)

CRS_DV (input)

Receive Error

RX_ER (output)

RX_ER (input)

Receive Data Bits [1:0]

RXD[1:0] (output)

RXD[1:0] (input)

TABLE 4-31:

RMII CONNECTION TO EXTERNAL PHY

RMII Interface Signals Description

KSZ9563R Signals

External PHY Device Signals

Transmit Enable

RX_DV (output)

TX_EN (input)

Transmit Data Bits [1:0]

RXD[1:0] (output)

TXD[1:0] (input)

Reference Clock

REFCLKI (input)

or REFCLKO (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

TX_EN (input)

CRS_DV (output)

Receive Error

No connection

RX_ER (output)

Receive Data Bits [1:0]

TXD[1:0] (input)

RXD[1:0] (output)

KSZ9563RNXI 数据表(PDF) 59 Page - Microchip Technology

KSZ9563RNXI 数据表(HTML) 59 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

KSZ9563RNXI 数据表(PDF) 59 Page - Microchip Technology

KSZ9563RNXI 数据表(HTML) 59 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载