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KSZ9563RNXI 数据表(PDF) 131 Page - Microchip Technology |
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KSZ9563RNXI 数据表(HTML) 131 Page - Microchip Technology |
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131 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 131 KSZ9563R 5.2.1.10 Port PME_WoL Enable Register 5.2.1.11 Port Interrupt Status Register These registers provide interrupt status for the individual ports. these interrupts are enabled in the Port Interrupt Mask Register. For non-port specific interrupt status, refer to the Global Interrupt Status Register. Address: 0xN017 Port N: 1-3 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_0b 2 Magic Packet Detect Enable To be detected, the destination address of the Magic Packet must match the Global Switch MAC Address in the Switch MAC Address 0 Register through Switch MAC Address 5 Register. 1 = The PME pin will be asserted when a Magic Packet is detected at this port 0 = The PME pin will not be asserted by Magic Packet detection at this port RO/WC 0b 1 Link Up Detect Enable Applicable only to ports with integrated PHY. 1 = The PME pin will be asserted when link up is detected at this port 0 = The PME pin will not be asserted by link up detection at this port RO/WC 0b 0 Energy Detect Enable Applicable only to ports with integrated PHY. 1 = The PME pin will be asserted when cable energy is detected at this port 0 = The PME pin will not be asserted by cable energy detection at this port RO/WC 0b Address: 0xN01B Port N: 1-3 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_00b 2 PTP Interrupt Status Applies only to PHY ports, not MAC port(s). Refer to the Port PTP Timestamp Interrupt Status Register for individual PTP interrupts. 0 = No interrupt 1 = Interrupt detected RO 0b 1 PHY Interrupt Status Applies only to PHY ports, not MAC port(s). Refer to the Port Interrupt Control / Status Register for individual PHY interrupts. 0 = No interrupt 1 = Interrupt detected RO 0b |
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