P9412 Datasheet

R35DS0011EU0120 Rev.1.2

Jul.6.21

Page 5

1.2

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

A1

SCL (OD1)

I/O

Clock for I2C Serial Interface with AP (SCL). Connect a pull-up resistor to the system I/O supply.

A2

nINT (OD3)

O

Open-drain GPIO; active-LOW interrupt from the P9412 to the AP. Connect an external pull-up to

V1P8_AP with a 10k

Ω - 100kΩ resistor. Output is active-LOW when status change occurs in the

interrupt registers.

A3

GPIO4

I/O

General purpose push-pull I/O, referenced to LDO1P8. May be left floating if unused.

A4

GPOD6

O

Ping Detect (PDET) output indicator and can be left floating if unused.

A5

GPIO2

I/O

General purpose push-pull I/O, referenced to LDO1P8. May be left floating if unused.

A6, A7, A8,

A9

CPGND

GND

Ground for capacitor divider. All CPGND pins must be connected together with PGND and GND

externally.

B1

SDA (OD2)

I/O

Data for I2C Serial Interface with AP (SDA). Connect a pull-up resistor to the system I/O supply.

B2

GPIO5

I/O

General purpose push-pull I/O, referenced to LDO1P8. It can be left floating if unused.

B3

GPOD4

I/O

General Purpose Open Drain I/O. Default state is configured as CPOUT_GD function. It can be

left floating if unused.

B4

GPOD5

I

Active High SW Inhibit input. When active the device will not connect wirelessly. Connect to GND

if unused.

B5

GPIO1

I

Reported Q-factor ADC input for EPP Rx mode. Connect to a resistor divider from LDO1P8 and

GND. Connect to GND if unused.

B6

CPBST1

O

Bootstrap capacitor connection to a CPN. Powers driver for NFET associated with CPN and

CPOUT.

B7, B8, B9

CPN

I/O

Capacitor Divider flying capacitor negative connection. Place two or three 22µF capacitors

between CPP and CPN pin.

C1, D1, D2,

D3, D4, D5,

E3, E4, J3

GND

GND

Ground. All GND pins must be connected together with PGND and CPGND externally.

C2

PCLAMP_

Dr

O

Output gate driver pin for External Clamping Circuit (5V IO level). May be left floating if unused

(only applicable for <15W designs). Connect as shown in reference design for >15W designs.

C3

GPIO3

I/O

General purpose push-pull I/O, referenced to LDO1P8. May be left floating if unused.

C4

GPOD0

I

Active low PDET enable input. Connect to GND if not used.

C5

GPIO0

I

Reported Q-factor ADC input for EPP Rx mode. Connect to a resistor divider from LDO1P8 and

GND. Connect to GND if unused (forces device to use register value to report Q in EPP Rx mode).

C6

CPBST2

O

Bootstrap capacitor connection to CPout. Powers driver for NFET associated with CPOUT and

CPP.

C7, C8, C9

CPOUT

I/O

Output of capacitor divider converter or MDLO in Bypass Configuration in Rx mode or input for

TRx mode. Connect to load switch and then to system load/TRx power supply and two 22µF

ceramic capacitors to GND.

D6

CPBST3

O

Bootstrap capacitor connection to CPP. Powers driver for NFET associated with CPP and CPout.

D7, D8, D9

CPP

I/O

Capacitor Divider flying capacitor positive connection. Place two or three 22µF capacitors

between CPP and CPN pin.

E1

nEN

I

Active-low enable pin. When it is pulled-up High by the AP GPIO, the rectifier will be set in Diode

mode, internal regulator do not activate, and firmware does not load. While it is pulled-down Low,

the device operates as programmed by firmware.

E2

DEMOD

I

Tx mode Communication Demodulator input. Connect to LC node via diode and DEMOD filter.

E5

VOUT_S

O

Main LDO output voltage sensing pin. Connect close to VOUT bypass capacitor with separate

connection from the MLDO VOUT output connection (pins E6-E9).