P9412 Datasheet

R35DS0011EU0120 Rev.1.2

Jul.6.21

Page 21

on the selected capacitors should be considered, and at least 6µF of effective capacitance at 5V DC is

recommended for proper device operation for power levels up to 5W. For 10W designs, the effective capacitance

should be at least 7.5µF at 10V DC. For 20V output levels, the effective capacitance at 20VDC should be 8µF. A

0.01µF capacitor in a 0201 or 0402 size package is recommended for high frequency decoupling of the VRECT

power rail. The voltage rating o

f these components should be ≥ 35V. Vrect capacitor is the input capacitor for

VOUT and is subject to high current events at the wireless power transfer operating frequency.

3.18

Output Capacitors (VOUT and CPOUT Capacitors)

The output capacitor connection to the ground pins (PGND) should be made as short as practical for maximum

device performance. Since the LDO has been designed to function with very low ESR capacitors, a ceramic

capacitor is recommended for best performance. For better transient response and lower output ripple voltages,

the total amount of output capacitance should be increased to meet the output voltage variation target of the

application (VRECT capacitance might need to be increased as well). The DC bias effects on the selected

capacitors should be considered, and at least 3µF of effective capacitance is required for all output voltages.

Additionally to improve performance it is recommended to have 4.5µF of effective capacitance at 10V DC output

and 5 µF for 20V DC output levels. A 2.2nF capacitor in a 0201 or 0402 size package is also necessary for high

frequency decoupling of the VOUT power rail.

The CPOUT node is a switching capacitive divider output capable of providing 2× the output current supplied by

VOUT at ½ the voltage. The Capacitive divider should have a bank of flying capacitors (3 × 22 µF), three

bootstrap capacitors and CPOUT bypass capacitors (2 × 10 µF). The output ripple will be a function of the

effective capacitance used for CFLY and CPOUT as well as the effective capacitance of Vrect and VOUT. A 1nF

capacitor in a 0201 or 0402 size package is recommended for high frequency decoupling of the CPOUT power

rail.

3.19

LDO1P8 Capacitor

The P9412 has an internal LDO regulator that must have at least a 1µF to 2.2µF capacitor connected from the

LDO1P8 pin to PGND. This capacitor should be as close as possible to the LDO1P8 pin with a close GND

connection. A 0.1µF capacitor in a 0201 or 0402 size package can be added for improved high frequency

decoupling of the LDO1P8 power rail since this voltage powers the internal ARM Cortex-M0 processor.

3.20

LDO5P0 Capacitor

The P9412 has an internal LDO regulator that must have at least a 1µF to 2.2µF capacitor connected from the

LDO5P0 pin to PGND. This capacitor should be as close as possible to the LDO5P0 pin with a close PGND

connection. A 0.1µF capacitor in a 0201 or 0402 size package can be added for improved high-frequency

decoupling of the LDO5P0 power rail since this voltage powers the internal ADC, gate drive supplies, and UVLO

circuits.

3.21

XY Alignment

The P9412 has integrated XY alignment coil data receive circuitry that should be used to monitor XY alignment

coils integrated with the WPC TRx coil. The XY alignment feature allows the device to sense its relative position

to the Tx coil magnetic field center and enables FOD compensation to be applied based on the position of the Rx

to increase spatial freedom. When used, the XY alignment coils should be connected to pins GP2 (X-alignment

coil input) and GP5 (Y-alignment coil input). For more information, see the P9412 User Manual and Application

Note P9412 XY Alignment Coil Design, Usage, and Tuning Guide.