P9412 Datasheet

R35DS0011EU0120 Rev.1.2

Jul.6.21

Page 11

Symbol

Description

Conditions

Minimum

Typical

Maximum

Unit

I2C SERIAL INTERFACE(NOTE2)

VIL

Input Low Threshold

VPull-Up = 1.8V

0.7

V

VIH

Input High Threshold

1.4

V

II2C_PINS_LKG

Leakage Current

V=1.8V, TA=25°C

±1

µA

VOL

Output Logic Low

IOL=8mA

0.36

V

fSCL

SCL & SCL_M Clock

Frequency

Cb=400pF (max)

400

kHz

Ci

Capacitance for each I/O pin

In fSCL=Max 400kHz

10

pF

tHD,STA

Hold Time (Repeated) for

START Condition

fSCL=Max 400kHz

0.6

µs

tHD:DAT

Data Hold Time

0

µs

tLOW

Low Period of the SCL clock

fSCL=Max 400kHz

1.3

µs

tHIGH

High Period of the SCL clock

fSCL=Max 400kHz

0.6

µs

tSU:STA

Set-up Time for Repeated

START Condition

fSCL=Max 400kHz

0.6

µs

tBUF

Bus Free Time Between

STOP and START Condition

1.3

µs

Cb

Capacitive Load for Each Bus

Line

fSCL=Max 400kHz

400

pF

1. The LDO1P8 pin can only be loaded after device startup.

2. Guaranteed by design and not fully tested in production.

3. Input voltage operating range is dependent upon the type of transmitter power stage (Full-bridge, half-bridge) and transmitting coil

inductance. WPC Specifications should be consulted for appropriate input voltage ranges by end-product type.

4. When Vout is set above 12V, firmware should turn on capacitor divider on into bypass mode with Vout =12V first and then increase the

Vout to the final value

5. Finer step size may be achieved by firmware.