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STRT71XF 数据表(PDF) 55 Page - STMicroelectronics |
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STRT71XF 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 74 page  STR71xF Electrical parameters 55/74 2.3.7 EMI - Memory Interface Subject to general operating conditions for VDD, fHCLK, and TA unless otherwise specified. The tables below use a variable which is derived from the EMI_BCONn registers (described in the STR71x Reference Manual) and represents the special characteristics of the programmed memory cycle. tres(TIM) Timer resolution time 1 tPCLK2 fPCLK2 = 30MHz 33.3 ns fEXT Timer external clock frequency fCK_TIM(MAX) = fMCLK 0 fCK_TIM/4 MHz fCK_TIM = fMCLK = 60MHz 015 MHz ResTIM Timer resolution 16 bit tCOUNTER 16-bit Counter clock period when internal clock is selected 1 65536 tPCLK fPCLK2 = 30MHz 0.033 2184 µs TMAX_COUNT Maximum Possible Count 65536x 65536 tPCLK fPCLK2 = 30MHz 143.1 s Table 30. TIM characteristics Symbol Parameter Conditions Min Typ Max Unit Table 31. EMI general characteristics Symbol Parameter Value tMCLK CPU clock period 1 / fMCLK tC Memory cycle time wait states tMCLK x (1 + [C_LENGTH]) |
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