STRT71XF datasheet(19/74 Pages) STMICROELECTRONICS

19 / 74 page

STR71xF

Introduction

19/74

The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 28.

The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends

on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset

In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured

by software as Alternate Function (see Table 7: Port Bit Configuration Table on page 28) to be used by the

External Memory Interface.

In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address

0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they

need to be configured by software as Alternate Function (see Table 7: Port Bit Configuration Table on

page 28).

V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected.

During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as

Output Push-Pull.

During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as

Hi-Z.

During the reset phase, these pins are in input pull-down state. When reset is released, they are configured

as Output Push-Pull.

During the reset phase, and after reset is released, this pin is in Output Push-Pull state.

143

P0.8/U0.RX/

U0.TX

I/O pd

CT X4mA T

Port 0.8

UART0:

Receive Data

input

UART0: Transmit

data output.

Note: This pin may be used for single wire UART

(half duplex) if programmed as Alternate Function

Output. The pin will be tri-stated except when

UART transmission is in progress

144

P0.9/U0.TX/

BOOT.0

I/O pd

4mA

Port 0.9

Select Boot

Configuration

input

UART0: Transmit

data output

Table 3.

STR710 Pin Description

Pin n°

Pin Name

Input

Output

Main

function

(after

reset)

Alternate function

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