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STRT71XF 数据表(PDF) 40 Page - STMicroelectronics |
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STRT71XF 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 74 page ![]() Electrical parameters STR71xF 40/74 2.3.2 Clock and timing characteristics External Clock Sources Subject to general operating conditions for V33, and TA. Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 14. CK External Clock Source Table 17. CK External Clock Characteristics Symbol Parameter Conditions Min Typ Max Unit fCK External clock source frequency 0 16.5 MHz VCKH CK input pin high level voltage 0.7xV33 V33 V VCKL CK input pin low level voltage VSS 0.3xV33 tw(CK) tw(CK) CK high or low time 1) 25 ns tr(CK) tf(CK) CK rise or fall time 1) 5 IL CK Input leakage current VSS≤VIN≤V33 ±1 µA CK fCLK EXTERNAL STR710 CLOCK SOURCE VCKL VCKH tr(CK) tf(CK) tw(CKH) tw(CKL) IL 90% 10% TCK |
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