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STRT71XF 数据表(PDF) 44 Page - STMicroelectronics |
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STRT71XF 数据表(HTML) 44 Page - STMicroelectronics |
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44 / 74 page  Electrical parameters STR71xF 44/74 Table 21. PLL2 Characteristics Symbol Parameter Test Conditions Value Unit Min Typ Max fPLLCLK2 PLL multiplier output clock fPLL x 28 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Table 22. Low-power Mode Wake-up Timing Symbol Parameter Typ Unit tWULPWFI Wake-up from LPWFI mode 26 µs tWUSTOP Wake-up from STOP mode 131 µs tWUSTBY Wake-up from STANDBY mode 2 µs |
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