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Design Considerations (Continued)

The low frequency pole is:

And the higher frequency pole is:

In the equation for A

PS, the output resistance, RO,isthe

output voltage divided by output current. DC gain is highest

when output current is lowest. In order to design for the worst

case, R

O should be calculated for the minimum load current.

For this example, no minimum load has been specified, so a

load of 100 mA will be used (R

O =10

Ω).

For this example, the value of DC gain is 24dB. The low

frequency pole f

P =2

πω

P is at 2.7kHz, the ESR zero fZ =

πω

Z is at 800 kHz, and the higher frequency pole is at

48kHz. Gain and phase plots for the power stage are shown

in Figure 8.

The low frequency pole and higher frequency pole cause a

roll-off in the gain of -20 dB/decade at lower frequency that

increases to -40 dB/decade at higher frequency. The effect

of the ESR zero is not seen because its frequency is beyond

the switching frequency. If this loop were left uncompen-

sated, the bandwidth would be 39 kHz and the phase margin

58˚. This loop would be stable, but would suffer from poor

regulation of the output voltage due to the low DC gain. In

practice, this loop could change significantly due to the

tolerances in the output inductor, output capacitor, changes

in output current, or input voltage. Therefore, the loop is

compensated using the error amplifier and a few passive

components.

In general the goal of the compensation circuit is to give high

DC gain, a bandwidth that is between one-fifth and one-tenth

of the switching frequency, and at least 45˚ of phase margin.

The majority of both peak current mode and emulated peak

current mode buck regulators can be compensated with just

two components, R

1 and C1, as shown in the Typical Appli-

cation circuit. For power stages where the ESR zero fre-

quency is below one-half of the switching frequency a sec-

ond capacitor, C

2, may be needed to add another pole to the

compensation. For power stages where the ESR zero fre-

quency is beyond the control loop bandwidth, a compromise

in bandwidth is needed to maintain good phase margin. The

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FIGURE 8. Power Stage Gain and Phase

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