LM3495MTC datasheet(16/26 Pages) NSC

16 / 26 page

Applications Information (Continued)

tion. During shutdown, both the high-side and low-side FETs

are disabled. The output voltage is discharged through the

SNS pin by an internal 500

Ω FET.

THERMAL SHUTDOWN

The LM3495 will enter a thermal shutdown state if the die

temperature exceeds 150˚C. Both the high-side and low-side

power FETs are turned off, the output voltage is discharged

through an internal 500

Ω FET, and the IC will remain in this

condition until the die temperature has dropped to approxi-

mately 135˚C. At this point the LM3495 will perform a soft-

start.

Design Considerations

The most common circuit controlled by the LM3495 is a

non-isolated, synchronous buck regulator. The buck regula-

tor steps down the input voltage and has a duty cycle, D, of:

The following is a design procedure for selecting all the

components in the Typical Application circuit on the front

page. This circuit delivers a 1.2V ± 1% output voltage at

output currents up to 10A from an input voltage of 12V ±

10%. This circuit is typical of a point-of-load (POL) module. A

BOM for this typical application is listed in Table 3 at the end

of this datasheet.

SWITCHING FREQUENCY

The selection of switching frequency is based on the

tradeoffs between size, cost, and efficiency. In general, a

lower frequency means larger, more expensive inductors

and capacitors will be needed. A higher switching frequency

generally results in a smaller but less efficient solution, as

the power FET gate capacitances must be charged and

discharged more often in a given amount of time. For this

application, a frequency of 500 kHz was selected because

the space on a POL circuit board is limited. This frequency is

a good compromise between the size of the inductor and

FETs, transient response, and efficiency. Following the

equation given for R

FRQ in the Applications Information sec-

tion, a 54.9 k

Ω 1% resistor should be used to switch at 500

kHz.

MOSFETS

Selection of the power FETs is governed by the same

tradeoffs as switching frequency. Breaking down the losses

in the high-side and low-side FETs is one way to determine

relative efficiencies between different FETs. When using dis-

crete SO-8 FETs the LM3495 is most efficient for output

currents of 2A to 10A.

Losses in the power FETs can be broken down into conduc-

tion loss, gate charging loss, and switching loss.

Conduction, or I

2R loss, P

C, is approximately:

C =D(IO

2 xR

DSON-HI x 1.3)

(High-Side MOSFET)

C =(1-D)x(IO

2 x(R

DSON-LO x1.3+RSNS))

(Low-Side MOSFET)

In the above equations R

DSON-HI and RDSON-LO refer to

on-resistance of the high-side and low-side FETs, respec-

tively. R

SNS is 0 if it is not used. The factor 1.3 accounts for

the increase in FET on-resistance due to heating. Alterna-

tively, the factor of 1.3 can be ignored and the on-resistance

of the FET can be estimated using the R

DSON vs Tempera-

ture curves in the FET datasheets. Gate charging loss, P

GC,

results from the current driving the gate capacitance of the

power FETs and is approximated as:

GC =nx(VLIN5 –VD)xQG-HI xfSW

(High-Side MOSFET)

GC =nxVLIN5 xQG-LO xfSW

(Low-Side MOSFET)

In the above equations Q

G-HI and QG-LO refer to the gate

charge of the high-side and low-side FETs, respectively. The

factor ‘n’ is the number of FETs (if multiple devices have

been placed in parallel) and Q

G is the total gate charge of the

FET. If different types of FETs are used, the ‘n’ term can be

ignored and their gate charges summed to form a cumulative

G. Gate charge loss differs from conduction and switching

losses in that the actual dissipation occurs in the LM3495

and not in the FET itself. Further loss in the LM3495 is

incurred as the gate driving current passes through the

internal linear regulator. This loss term is factored into the

Chip Operating Loss portion of the Efficiency Calculations

section.

Switching loss, P

SW, occurs during the brief transition period

as the FET turns on and off. During the transition period both

current and voltage are present in the channel of the FET.

The loss can be approximated as:

SW =0.5xVIN xIO x(tR +tF)xfSW

Where t

R and tF are the rise and fall times of the FET.

Switching loss is calculated for the high-side FET only.

Switching loss in the low-side FET is negligible because the

body diode of the low-side FET turns on before the FET

itself, minimizing the voltage from drain to source before

turn-on.

For this example, the maximum drain-to-source voltage ap-

plied to either FET is 13.2V. The maximum drive voltage at

the gate of the high-side FET is 4.5V, and the maximum drive

voltage for the low-side FET is 5V. Any FET selected must be

able to withstand 13.2V plus any ringing from drain to

source, and be able to handle at least 5V plus ringing from

gate to source. One good choice of FET for the high-side has

an R

DSON of 9.6 m

Ω, total gate charge Q

G of 11 nC, and rise

and fall times of 5 and 8 ns, respectively. For the low-side

FET, a good choice has an R

DSON of 3.4 m

Ω and gate

charge of 33 nC. These values have been taken from the

FET datasheets with a V

GS of 4.5V.

OUTPUT INDUCTOR

The first criterion for selecting an output inductor is the

inductance itself. In most buck converters, this value is

based on the desired ripple current,

∆i

O, which flows in the

inductor along with the load current. This ripple current will

flow through the ESR and impedance of the output capacitor

to create the output voltage ripple,

∆v

O. Due to the unique

control architecture of the LM3495, a second requirement for

LM3495MTC 数据表(PDF) 16 Page - National Semiconductor (TI)

LM3495MTC 数据表(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表下载