apply over the full Operating Junction Temperature (T

design, or statistical correlation. Typical values represent the most likely parametric norm at T

reference purposes only. Unless otherwise indicated, V

Symbol

Parameter

Conditions

Min

Typ

(Note

4)

Max

Units

R

DS3

Low-Side FET Driver Pull-up ON

resistance

VLIN5 = 5.5V

1.4

Ω

R

DS4

Low-Side FET Driver Pull-down ON

resistance

VLIN5 = 5.5V

0.7

Ω

OSCILLATOR

f

SW

PWM Frequency

R

Ω

200

kHz

R

Ω

450

500

550

R

Ω

1500

V

SYNC-HI

Threshold for SYNC on FREQ Pin

SYNC Voltage Rising

1.2

V

V

SYNC-LO

Threshold for SYNC on FREQ Pin

SYNC Voltage Falling

0.3

V

t

ON-SKIP

On Time During Skip Mode

V

f

125

ns

t

ON-MAX

Adaptive Maximum On-time Limit

V

f

750

ns

t

OFF-MIN

Minimum Off-time

300

ns

ERROR AMP

g

M

Transconductance

750

µmho

BW

-3dB

Open Loop Bandwidth

COMP/SD Floating

5

MHz

I

FB

FB Pin Bias Current

V

1

nA

I

SOURCE

COMP/SD Pin Source Current

V

40

µA

I

SINK

COMP/SD Pin Sink Current

V

40

µA

V

COMP-HI

COMP/SD Pin Voltage High Clamp

V

2

V

V

COMP-LO

COMP/SD Pin Voltage Low Clamp

V

0.9

V

TRACKING

V

TEND

Track End Threshold

0.6

V

V

TRACK-OS

Track to FB Offset

TRACK = 0.55V

15

mV

INTERNAL VOLTAGE REGULATOR

V

VLIN5

Voltage at VLIN5 Pin (Note 3)

V

4.72

V

V

3.0

V

LOGIC INPUTS AND OUTPUTS

V

SD-HI

COMP/SD Pin Logic High Trip Point

COMP/SD Pin Voltage Rising

0.3

0.4

V

V

SD-LO

COMP/SD Pin Logic Low Trip Point

COMP/SD Pin Voltage Falling

0.2

0.26

V

THERMAL CHARACTERISTICS

θ

JA

Junction-to-Ambient Thermal

Resistance

155

˚C/W

T

SD

Thermal Shutdown Threshold

150

˚C

T

SD-HYS

Thermal Shutdown Hysteresis

15

˚C

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device

is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.

Note 3: VLIN5 provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

Note 4: Typical specifications represent the most likely parametric norm at 25˚C operation.

Note 5: An extended negative voltage limit of –2V applies for a duration of 20 ns per switching cycle

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