LM3495MTC datasheet(13/26 Pages) NSC

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Applications Information (Continued)

output voltage of the master supply. In this case, the tracking

resistors can be determined based on the following equa-

tion:

Again, a value of 10 k

Ω 1% is recommended for R

T2. For the

example case of V

OUT1 = 5V and VOUT2 = 1.8V, RT1 would

be 5.62 k

Ω 1%. A timing diagram for this example, the case

of equal slew rates, is shown in Figure 3.

FPWM MODE OPERATION

The LM3495 operates under forced PWM when the FPWM

pin is connected to ground. While in FPWM operation, the

LM3495 controls the output voltage by adjusting the duty

cycle of the power FETs with trailing edge PWM. The output

inductor and capacitor filter the square wave produced as

the power FETs chop the input voltage, thereby creating a

regulated output voltage. The DC level of the output voltage

can be set anywhere from 0.6V up to 5.5V, and is deter-

mined by a pair of feedback resistors using the following

equation:

In steady state FPWM mode, the inductor current can flow

from the drain to the source of the low-side FET, keeping the

converter in continuous conduction mode (CCM) at all times.

CCM has the advantage of constant frequency and nearly

constant duty cycle (D = V

O/VIN) over all load conditions, and

it allows the converter to sink current at the output if needed.

The switching frequency of the internal oscillator is set by a

resistor, R

FRQ,

connected from the FREQ/SYNC pin to

ground. The proper resistor for a desired switching fre-

quency, f

SW, can be determined by using the following equa-

tion:

SKIP MODE OPERATION

If the FPWM pin is left open-circuited, the LM3495 can enter

into SKIP mode operation, delivering better efficiency at light

loads. As long as the inductor current is positive (flowing

from the switch node to the output node), SKIP mode is

identical to FPWM mode. Once the inductor current be-

comes negative, however, an internal zero-cross comparator

will disable the low-side FET. This ’diode-emulation’ mode

allows the converter to operate in discontinuous conduction

mode (DCM). In DCM, the duty cycle decreases as the load

current decreases. A minimum on-time comparator prevents

the duty cycle during DCM from decreasing below 80% of

the steady state duty cycle, D. The converter will allow one

on-time pulse, causing the output voltage to rise and the

COMP/SD voltage to droop. If COMP/SD drops below the

skip cycle comparator threshold of 1.05V, the control logic

will disable the high-side FET for one cycle, effectively skip-

ping a pulse. This skipping action continues until the

COMP/SD voltage rises above the skip cycle threshold.

Multiple pulses can be skipped depending on load, input

voltage, and output voltage. Switching frequency is not fixed

during SKIP Mode, but energy is saved because the high

and low-side FETs are driven less frequently than in FPWM

mode. In SKIP mode the regulator cannot sink current at the

output.

SKIP TO FPWM TRANSITION

The LM3495 employs circuitry to transition from SKIP mode

to FPWM mode with minimal discontinuity in inductor current

and output voltage. When the FPWM pin is grounded, the

threshold of the zero-cross comparator decreases from 0V

to -9.9 mV over fifteen switching cycles. After fifteen cycles

have elapsed, the zero-cross comparator is disabled entirely

and the circuit switches to FPWM mode.

Note that "on-the-fly" changes from FPWM mode to SKIP

mode are not recommended due to the possibility of discon-

tinuity in the inductor current and/or output voltage.

FREQUENCY SYNCHRONIZATION

The switching action of the LM3495 can be synchronized to

external clocks or other fixed frequency signals in the range

of 200 kHz to 1.5 MHz. The external clock should be applied

through a 100 pF coupling capacitor, C

SYNC, as shown in

Figure 4. In order for the LM3495 to synchronize properly,

the external clock should exceed 1.2V on each rising edge

and remain above 1.2V for at least 100 ns.

The external clock should also fall below 0.3V on each falling

edge, and remain below 0.3V for at least 100 ns. Circuits that

use an external clock should still have a resistor, R

FRQ,

connected from the FREQ/SYNC pin to signal ground. R

FRQ

should be selected using the equation from FPWM Mode

Operation to match the external clock frequency. This allows

the regulator to continue operating at approximately the

same switching frequency if the external clock fails and the

coupling capacitor on the clock side is grounded or pulled to

a logic high.

If the external clock fails low, timeout circuits will prevent the

high-side FET from staying off for longer than 1.5 times the

switching period (Switching period T

SW = 1/fSW). At the end

of this timeout period the regulator will begin to switch at the

frequency set by R

FRQ.

If the external clock fails high, timeout circuits will again

prevent the high-side FET from staying off longer than 1.5

times the switching period. After this timeout period, the

internal oscillator takes over and switches at a fixed 1 MHz

until the voltage on the FREQ/SYNC pin has decayed to

20169933

FIGURE 3. Tracking with Equal Slew Rates

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