LM3495MTC datasheet(14/26 Pages) NSC

14 / 26 page

Applications Information (Continued)

approximately 0.6V. This decay follows the time constant of

SYNC and RFRQ, and once it is complete the regulator will

switch at the frequency set by R

FRQ.

Care must be taken to prevent errant pulses from triggering

the synchronization circuitry. In applications that will not

synchronize to an external clock, C

SYNC should be con-

nected from the FREQ/SYNC pin to signal ground as a noise

filter. When a clock pulse is first detected, the LM3495

begins switching at the external clock frequency. Noise or a

short burst of clock pulses can result in off times as long as

7.5 µs for the high-side FET if they occur while the internal

synchronization circuits are adjusting.

MOSFET GATE DRIVE

The LM3495 has two gate drivers designed for driving

N-channel MOSFETs in a synchronous mode. Power for the

high-side driver is supplied through the BOOST pin. For the

high-side gate drive to fully turn on the top FET, the BOOST

pin voltage must be at least one threshold voltage, V

GS(th),

greater than V

IN. This voltage is supplied from a local charge

pump structure which consists of a Schottky diode and 0.1

µF capacitor, shown in Figure 5.

Both the bootstrap and the low-side FET driver are fed from

VLIN5, which is the output of a 4.7V internal linear regulator.

This regulator has a dropout voltage of approximately 1V. If

IN drops below 4V, an internal switch shorts the VIN and

VLIN5 pins together. The drive voltage for the top FET driver

is therefore VLIN5-V

D, where VD is the drop across the

Schottky diode D1. This information is needed to select the

type of MOSFETs to be used.

INPUT VOLTAGE BELOW 5.5V

The LM3495 includes an internal 4.7V linear regulator con-

nected from the VIN pin to the VLIN5 pin. This linear regu-

lator feeds the logic and FET drive circuitry. For input volt-

ages less than 5.5V, the VIN and VLIN5 pins can be shorted

together externally. The external short circuit bypasses both

the internal linear regulator and the internal PMOS switch,

allowing the full input voltage to be used for driving the power

FETs and minimizing conduction loss in the LM3495 itself.

For voltage inputs that range above and below 5.5V the

LM3495 must not use a short from VIN to VLIN5.

UNDER VOLTAGE LOCK-OUT

The 2.6V turn-on threshold on the voltage at VIN has a built

in hysteresis of 300 mV. If input voltage drops below 2.3V the

chip enters under voltage lock-out (UVLO) mode. UVLO

consists of turning off both the top and bottom FETs and

remaining in that condition until input voltage rises above

2.6V.

BOOTSTRAP DIODE SELECTION

Schottky diodes are the preferred choice for the bootstrap

circuit because of their low forward voltage drop. For circuits

that will operate at high ambient temperature the Schottky

diode datasheet must be read carefully to ensure that the

reverse leakage current at high temperature does not in-

crease enough to deplete the charge on the bootstrap ca-

pacitor while the high-side FET is off. Some Schottky diodes

increase their reverse leakage by as much as 1000x at their

upper temperature limit. Fast recovery and PN junction di-

odes maintain low reverse leakage even at high ambient

temperature. For high ambient temperature operation Schot-

tky diodes with guaranteed low leakage across temperature

or fast recovery type diodes should be used.

OVER VOLTAGE PROTECTION

The LM3495 will shut down if the output voltage exceeds

125% of the steady state target voltage for longer than 4 µs.

The high-side FET is turned off and the low-side FET is

turned on. The LM3495 will remain in this condition until

either the VIN pin voltage is cycled to ground, or the

COMP/SD pin voltage is pulled to below 0.3V and then

released. Either of these reset mechanisms will cause the

device to perform a soft-start.

LOW-SIDE CURRENT LIMIT

The current limit of the LM3495 operates by sensing the

current in the low-side FET while the load current, I

O, circu-

lates through it. The low-side FET drain-to-source voltage,

DS, is compared against the voltage of a fixed, internal 20

µA current source and a user-selected resistor, R

ILIM. The

value of R

ILIM for a desired current limit threshold, ICL, can

be selected with the following equation:

ILIM is connected between the switch node and the ILIM

pin. A current limit event is sensed when V

DS exceeds VILIM.

ILIM =20µA x RILIM). The high-side switch is disabled for

the following cycle and the low-side FET is kept on during

this time.

During long duration current limit conditions or a short circuit

the output voltage droops. This in turn causes the COMP/SD

pin voltage to rise. If the COMP/SD pin voltage exceeds 2V

20169936

FIGURE 4. Clock Synchronization Circuit

20169937

FIGURE 5. Bootstrap Circuit

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