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AM69AX 数据表(PDF) 111 Page - Texas Instruments |
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AM69AX 数据表(HTML) 111 Page - Texas Instruments |
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111 / 299 page  Table 6-88. PCIE Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] PCIE_REFCLK3_N_OUT O SERDES_PCIE Reference Clock Out Negative AP7 PCIE_REFCLK3_P_OUT O SERDES_PCIE Reference Clock Out Positive AP8 6.3.20 SERDES 6.3.20.1 MAIN Domain Table 6-89. SERDES0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES0_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AU9 SERDES0_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AU8 SERDES0_REXT (1) I External Calibration Resistor AN11 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 6-90. SERDES1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES1_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV3 SERDES1_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV4 SERDES1_REXT (1) I External Calibration Resistor AL9 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 6-91. SERDES2 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES2_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV21 SERDES2_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV22 SERDES2_REXT (1) IO External Calibration Resistor AL20 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. Table 6-92. SERDES4 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] SERDES4_REFCLK_N IO Serdes Reference Clock Input/Output (negative) AV16 SERDES4_REFCLK_P IO Serdes Reference Clock Input/Output (positive) AV15 SERDES4_REXT (1) IO External Calibration Resistor AM19 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. 6.3.21 DSI 6.3.21.1 MAIN Domain Table 6-93. DSI0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] CSI0_TXCLKN O CSI Differential Transmit Clock Output (negative) AP26 CSI0_TXCLKP O CSI Differential Transmit Clock Output (positive) AP25 CSI0_TXN0 O CSI Differential Transmit Output (negative) AU27 CSI0_TXN1 O CSI Differential Transmit Output (negative) AT26 CSI0_TXN2 O CSI Differential Transmit Output (negative) AR27 CSI0_TXN3 O CSI Differential Transmit Output (negative) AN24 CSI0_TXP0 O CSI Differential Transmit Output (positive) AU26 CSI0_TXP1 O CSI Differential Transmit Output (positive) AT25 CSI0_TXP2 O CSI Differential Transmit Output (positive) AR26 www.ti.com AM69A SPRSP92 – FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: AM69A |
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