Table 15. 400 kHz AC characteristics

Symbol

Alt.

Parameter

Min.

Max.

Unit

fC

fSCL

Clock frequency

-

400

kHz

tCHCL

tHIGH

Clock pulse width high

600

-

ns

tCLCH

tLOW

Clock pulse width low

1300

-

tQL1QL2(1)

tF

SDA fall time

20(2)

300

tXH1XH2

tR

Input signal rise time

(3)

(3)

tXL1XL2

tF

Input signal fall time

(3)

(3)

tDXCH

tSU:DAT

Data in setup time

100

-

tCLDX

tHD:DAT Data in hold time

0

-

tCLQX(4)

tDH

Data out hold time

100

-

tCLQV(5)

tAA

Clock low to next data valid (access time)

-

900

tCHDL

tSU:STA

Start condition setup time

600

-

tDLCL

tHD:STA

Start condition hold time

600

-

tCHDH

tSU:STO Stop condition setup time

600

-

tDHDL

tBUF

Time between Stop condition and next Start condition

1300

-

tW

tWR

Write time

-

5

ms

tNS(1)

-

Pulse width ignored (input filter on SCL and SDA), single glitch

-

100

ns

1. Characterized only, not tested in production.

2. With CL = 10 pF.

3. There are no minimum or maximum values for the input signal rise and fall times. It is however recommended by the I²C

specification that the input signal rise and fall times are between 20 and 300 ns when fC < 400 kHz.

4. The minimum value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region

of the falling edge SCL.

5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that Rbus x Cbus time constant is within the values specified in Figure 12.

M24C16-W M24C16-R M24C16-F

DC and AC parameters

DS9194 - Rev 11

page 21/40