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M24C16-R 数据表(PDF) 35 Page - STMicroelectronics

部件名 M24C16-R
功能描述  16-Kbit serial I2C bus EEPROM
PDF  40 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24C16-R 数据表(HTML) 35 Page - STMicroelectronics

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Date
Revision
Changes
18-Feb-2015
6
Removed: WLCSP package reference, tables and figures in all document
Updated: Table 54 and Table 70
01-Jul-2015
7
Updated: Section 6, Table 70
Added note 1 on Table 70
18-Mar-2016
8
Updated Features, Figure 41: Read mode sequences, Figure 51: UFDFPN5 – 1.7x1.4
mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package outline
and Table 53: UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat
package, no lead - package mechanical data
02-Oct-2017
9
Added reference to DFN8 and DFN5 in:
cover page figure, Figure 3: UFDFPN5 (DFN5) package connections
Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2: UFDFPN8 (DFN8)
package information.
Updated Table 9: AC measurement conditions, Table 23: Ordering information scheme.
Added Figure 14: UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine
pitch dual flat package, no lead recommended footprint
04-Jun-2020
10
Updated:
Section Features
Figure 4. Block diagram
Table 4. Absolute maximum ratings,
title of Table 7. Operating conditions (voltage range F)
notes in: Table 10. Cycling performance, Table 11. Memory cell data retention,
Table 12. DC characteristics (M24C16-W, device grade 6)Table 13. DC
characteristics (M24C16-R device grade 6), Table 14. DC characteristics (M24C16-
F device grade 6)
Removed Package PDIP8 in whole document, Table 8. Operating conditions (voltage
range F, for all other devices)
Added specification in Wafer thickness feature of Table 22. Ordering information scheme
(unsawn wafer)
12-Oct-2020
11
Updated Section Features and Section 1 Description.
Added note in Section 5.1.3 Minimizing write delays by polling on ACK.
Updated Table 21. Ordering information scheme and Table 22. Ordering information
scheme (unsawn wafer).
Updated Figure 1. Logic diagram.
Minor text edits across the whole document.
M24C16-W M24C16-R M24C16-F
DS9194 - Rev 11
page 35/40



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