5.1.6

Minimizing write delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from

its internal latches to the memory cells. The maximum write time (tw) is shown in AC characteristics tables in

Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 9, is:

•

Initial condition: a write cycle is in progress.

•

Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new

instruction).

•

Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back

to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the

device is ready to receive the second part of the instruction (the first byte of this instruction having been

sent during Step 1).

Figure 9. Write cycle polling flowchart using ACK

Write cycle

in progress

Next

operation is

addressing the

memory

Start condition

ACK

returned

YES

NO

YES

NO

Re-start

Stop

Data for the

write operation

Send address

and receive ACK

YES

NO

Continue the

write operation

Continue the

random read operation

Device select

with RW = 1

First byte of instruction

with RW = 0 already

decoded by the device

Device select

with RW = 0

StartCondition

1.

The seven most significant bits of the device select code of a random read (bottom right box in the figure)

must be identical to the seven most significant bits of the device select code of the write (polling instruction

in the figure).

M24M02-DR M24M02-R

Write operations

DS7025 - Rev 11

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