IMX8MPCEC datasheet(20/111 Pages) NXP

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i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.1.2

Thermal resistance

3.1.2.1

15 x 15 mm FCPBGA package thermal characteristics

Table 11 displays the 15 x 15 mm FCPBGA package thermal resistance data.

3.1.3

Power architecture

The power architecture of the chip is defined based on the assumption that lowest-cost system are

constructed for case where the PMIC is always used to supply all the power rails to the processor.

The digital logic inside chip will be supplied with two supplies: VDD_ARM and VDD_SOC.

•

VDD_ARM is for the Cortex®-A53 platform.

•

VDD_SOC is for the rest of the modules in SoC.

The VDD_SOC can be nominal or overdrive voltage, the VDD_ARM can be nominal, overdrive or

super-overdrive. To support system with VDD_ARM at super-overdrive voltage, it is recommended to use

two external DCDC or DC-DC supplies, first one for VDD_ARM and the second one for VDD_SOC.

However, for cost-optimized solutions, the two supplies can be tied together in customer systems.

VDD_ARM can support DVFS for SoCs that choose to enable it. VDD_SOC does not support fast

on-the-fly DVFS, but can support mode-based dynamic voltage for SoCs that choose to enable it.

The GPIO pads will have external power supply for 3.3 V and 1.8 V IO voltage. The IO pad core voltage

will be supplied directly by VDD_SOC. For 3.3 V IO pad, its 3.3 V IO supply (NVCC) and 1.8 V

pre-driver supply (PVCC_1P8) should be always meet NVCC - PVCC < 2 V requirement during power

up and power down. For 1.8 V IO pad, its 1.8 V PVCC can be shorted together with NVCC.

The DRAM controller and PHY have four external power supplies: VDD_SOC supplies controller and

PHY digital logic, VDD_DRAM_PLL_1P8 / VDD_DRAM_PLL_0P8 for PHY analog circuit, and

NVCC_DRAM for IO.

For all the integrated analog modules, their 1.8 V analog power and 0.85 V/0.95 V digital power will be

supplied externally through power pads. These supplies are separated with other power pads on the

Table 11. 15 x 15 mm FCPBGA thermal resistance data

Rating1

1 The ratings were generated using a non-uniformly powered die.

Board Type2

2 Thermal test board meets JEDEC specification for this package (JESD51-9). PCB has no thermal vias under the package.

Symbol

Value

Unit

Junction to Ambient Thermal Resistance3

3 Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not

meant to predict the performance of a package in an application-specific environment.

JESD51-9, 2s2p

RJA

21.1

oC/W

Junction-to-Top of Package

Thermal Characterization parameter3

JESD51-9, 2s2p

JT

0.98

oC/W

Junction to Case Thermal Resistance4

4 Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers t the package top

side surface.

JESD51-9, 1s

RJC

0.24

oC/W

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