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IMX8MPCEC 数据表(PDF) 1 Page - NXP Semiconductors

部件名 IMX8MPCEC
功能描述  i.MX 8M Plus Applications Processor Datasheet for Consumer Products
PDF  111 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

IMX8MPCEC 数据表(HTML) 1 Page - NXP Semiconductors

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NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MPCEC
Rev. 0, 03/2021
Ordering Information
See Table 3 on page 7
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
© 2021 NXP B.V.
MIMX8ML8DVNLZAB
MIMX8ML6DVNLZAB
MIMX8ML4DVNLZAB
MIMX8ML3DVNLZAB
Package Information
Bare die Package
FCBGA 15 x 15 mm, 0.5 mm pitch
1
i.MX 8M Plus introduction
The i.MX 8M Plus family focuses on neural processing
unit (NPU) and vision system, advance multimedia, and
industrial automation with high reliability.
The i.MX 8M Plus is a powerful quad Arm® Cor-
tex®-A53 processor with speed up to 1.8 GHz inte-
grated with a NPU of 2.3 TOPS that greatly accelerate
machine learning inference. The vision engine is com-
posed of two camera inputs and a HDR-capable Image
Signal Processor (ISP) capable of 375 MPixels/s.
The advanced multimedia capabilities include 1080p60
video encode and decode H.265 and H.264. A 3D and
2D graphic acceleration supporting 1 GPixel/s,
OpenVG 1.1, Open GL ES3.1, Vulkan, and Open CL
1.2 FP. Multiple audio and microphone interfaces for
Immersive Audio and Voice systems.
For industrial applications, real time control is enabled
by an integrated 800 MHz Arm® Cortex®-M7. Robust
control networks are possible via CAN-FD interfaces.
And a dual Gb Ethernet, one supporting Time Sensitive
Networking (TSN), drive gateway applications with low
latency. High industrial system reliability for safety is
leveraged by DRAM Inline ECC as well as ECC sup-
port on internal software-accessible SRAMs.
i.MX 8M Plus Applications
Processor Datasheet for
Consumer Products
1.
i.MX 8M Plus introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.
Ordering information . . . . . . . . . . . . . . . . . . . . . . . 7
2.
Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.
Unused input and output guidance . . . . . . . . . . . 14
3.
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.
Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 18
3.2.
Power supplies requirements and restrictions . . . 34
3.3.
PLL electrical characteristics . . . . . . . . . . . . . . . . 36
3.4.
I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.
I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 39
3.6.
Output buffer impedance parameters . . . . . . . . . 41
3.7.
System modules timing . . . . . . . . . . . . . . . . . . . . 43
3.8.
External peripheral interface parameters . . . . . . 45
4.
Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.
Boot mode configuration pins . . . . . . . . . . . . . . . 85
4.2.
Boot device interface allocation . . . . . . . . . . . . . . 85
5.
Package information and contact assignments . . . . . . . 87
5.1.
15 x 15 mm package information . . . . . . . . . . . . 87
5.2.
DDR pin function list . . . . . . . . . . . . . . . . . . . . . 106
6.
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110


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