IMX8MPCEC datasheet(6/111 Pages) NXP

6 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

i.MX 8M Plus introduction

1.1

Block diagram

Figure 1 shows the functional modules in the i.MX 8M Plus processor system.

Figure 1. i.MX 8M Plus system block diagram

System Control

Smart DMA x3

Temperature Sensor

Secure JTAG

Watchdog x3

Display

HDMI 2.0a Tx (eARC)

PWM x4

Machine Learning

MIPI-DSI 4-lane with PHY

External Memory

Security

TrustZone

DRM Ciphers

Secure Clock

eFuse Key Storage

Random Number

32 KB Secure RAM

Main CPU Platform

Dual/Quad Cortex-A53

32 KB I-cache

32 KB D-cache

NEON

FPU

512 KB L2 Cache (ECC)

HiFi 4

Cortex-M7

x32 LPDDR4/DDR4

LVDS Tx (4-lane or 8-lane)

Timer x6

XTAL

PLLs

SDIO 3.0 x3/MMC5.1 x2

NAND Controller (BCH62)

Neural Processing Unit: 2.3 TOPS

Secondary Cores

Graphics

3D Graphics: GC7000UL

2D Graphics: GC520L

Video

1080p60 H.265, H.264, VP9, VP8 decoder

1080p60 H.265, H.264 encoder

Vision

Camera ISP 2x 187 MP/1x 375 MP dewarp

MIPI-CSI 4-lane with PHY x2

Dual-ch QuadSPI (XIP) or

Audio

I2S TDM (32b @768 kHZ) x18

SPDIF Rx and Tx

8ch PDM Microphone Input

Connectivity and I/O

USB 3.0/2.0 with PHY x2

1 Gb Eth with TSN

(IEEE 1588 and AVB)

PCIe Gen3 x1

UART x4 (5 Mbps), I2C x6, SPI x3

eARC (HDMI)

ASRC

1 Gb Eth

(IEEE 1588, EEE, and AVB)

OctalSPI (XIP) x1

1-lane L1 Substates

with PHY x1

868 KB OCRAM

Temperature Probe x2

FlexCAN x2

Image Sensor Interface

(Inline ECC)

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