IMX8MPCEC datasheet(21/111 Pages) NXP

21 / 111 page

Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

package to keep them clean, but they can be directly shared with other power rails on the board to reduce

the number of power supplies from the PMIC.

For all the integrated PCIe PHY, LVDS PHY, MIPI PHY, and USB PHY, their 3.3 V (where supported),

1.8 V and 0.85/0.95 V power will be supplied externally through power pads. The powers to those PHYs

are separated with other power pads on the package to keep them clean, but they can be directly shared

with other power rails on the board to reduce the number of power supplies from the PMIC. A LDO will

be integrated to generate the 1.2 V required for the MIPI PHY. The MIPI PHY also has integrated within

its PHY and LDO to generate its 0.4V supply. External capacitors are required for both the 1.2 V and 0.4

V internal LDO regulators.

For SNVS/RTC, the 1.8 V IO pre-driver supply and 1.8 V IO pad supply will also be supplied externally.

The 0.8 V SNVS_LP core domain logic is supplied by an internal LDO.

Figure 3 is the power architecture diagram. Note it only shows supplies, and does not show capacitors that

may be required for internal LDO regulators.

IMX8MPCEC 数据表(PDF) 21 Page - NXP Semiconductors