STM32G0C1NET6XTR datasheet(17/159 Pages) STMICROELECTRONICS

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DS13564 Rev 4

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STM32G0C1xC/xE

Functional overview

3.7

Power supply management

3.7.1

Power supply schemes

The STM32G0C1xC/xE devices require a 1.7 V to 3.6 V operating supply voltage (VDD).

Several different power supplies are provided to specific peripherals:

•

VDD = 1.7 (1.6) to 3.6 V

VDD is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold

VPOR(max). Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold VPDR(min).

•

VDDA = 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

VDDA is the analog power supply for the A/D converter, D/A converter, voltage

reference buffer and comparators. VDDA voltage level is identical to VDD voltage as it is

provided externally through VDD/VDDA pin.

•

VDDIO1 = VDD

VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage

as it is provided externally through VDD/VDDA pin.

•

VDDIO2 = 1.6 to 3.6 V

VDDIO2 is the power supply from VDDIO2 pin for selected I/Os and VDDUSB. On

packages without VDDIO2 pin, VDDUSB and VDDIO2 are internally connected with VDD.

Although VDDIO2 is independent of VDD or VDDA, it must not be applied without valid

VDD.

•

VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC,

TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not

present. VBAT is provided externally through VBAT pin. When this pin is not available

on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

•

VREF+ is the analog peripheral input reference voltage, or the output of the internal

voltage reference buffer (when enabled). When VDDA < 2 V, VREF+ must be equal to

VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be grounded

when the analog peripherals using VREF+ are not active.

The internal voltage reference buffer supports two output voltages, which is configured

with VRS bit of the VREFBUF_CSR register:

–VREF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V)

–VREF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V)

VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is

internally connected with VDD, and the internal voltage reference buffer must be kept

disabled (refer to datasheets for package pinout description).

•

VCORE

An embedded linear voltage regulator is used to supply the VCORE internal digital

power. VCORE is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with VDD.

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