STM32G0C1NET6XTR datasheet(24/159 Pages) STMICROELECTRONICS

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Functional overview

STM32G0C1xC/xE

24/159

DS13564 Rev 4

3.13

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called

exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

and an extended interrupt/event controller (EXTI) are the assets contributing to handling the

exceptions. Exceptions include core-internal events such as, for example, a division by zero

and, core-external events such as logical level changes on physical lines. Exceptions result

in interrupting the program flow, executing an interrupt service routine (ISR) then resuming

the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon

program interrupt and unstacked upon program resume, by hardware. This avoids context

stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving

time, code and power. The ability to abandon and restart load-multiple and store-multiple

operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1

Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It

handles physical line events associated with a non-maskable interrupt (NMI) and maskable

interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between

interrupt events and start of corresponding interrupt service routines (ISRs). The ISR

vectors are listed in a vector table, stored in the NVIC at a base address. The vector

address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring

just before is waiting for being served, the later-arriving higher-priority interrupt event is

served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

ISR then start of a pending lower-priority ISR, the unnecessary processor context

unstacking and stacking is skipped. This reduces latency and contributes to power

efficiency.

Features of the NVIC:

•

Low-latency interrupt processing

•

4 priority levels

•

Handling of a non-maskable interrupt (NMI)

•

Handling of 32 maskable interrupt lines

•

Handling of 10 Cortex-M0+ exceptions

•

Later-arriving higher-priority interrupt processed first

•

Tail-chaining

•

Interrupt vector retrieval by hardware

3.13.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and

allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising,

and falling edge detector capability. Any GPIO and a few peripheral signals can be

connected to these channels.

STM32G0C1NET6XTR 数据表(PDF) 24 Page - STMicroelectronics

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