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STM32G0C1NET3X 数据表(PDF) 13 Page - STMicroelectronics |
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STM32G0C1NET3X 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 159 page  DS13564 Rev 4 13/159 STM32G0C1xC/xE Description 36 Figure 1. Block diagram MSv63192V2 FDCAN1 & 2 I2C2 SPI1/I2S LPUART& & 2 UCPD AES RNG USART3/4 LPTIMER 1/2 TIMER 16/17 Power domain of analog blocks : VBAT 4 channels BKIN, BKIN2, ETR System and peripheral clocks MOSI/SD MISO/MCK SCK/CK NSS/WS SWCLK SWDIO 16x IN OSC_IN OSC_OUT VBAT OSC32_IN OSC32_OUT RTC_OUT RTC_REFIN RTC_TS MOSI, MISO SCK, NSS VDD IR_OUT 1 channel BKIN ETR, IN, OUT 1 channel 4 channels ETR 4 channels ETR CPU CORTEX-M0+ fmax = 64 MHz SWD NVIC EXTI SPI/I2S 1 & 2 SPI3 AHB-to-APB RCC Reset & clock control I/F XTAL OSC 4-48 MHz IWDG I/F ADC RTC, TAMP Backup regs I/F XTAL32 kHz VDD 2 channels BKIN RX, TX CTS, RTS CEC TIM6 TIM7 COMP1 COMP2 IN+, IN-, OUT VDDA SUPPLY SUPERVISION POWER VCORE POR Reset Int VDD/VDDA VSS/VSSA NRST PVD POR/BOR Voltage regulator USART1 to 6 LPTIM1 & 2 TIM16 & 17 TIM15 TIM14 TIM3 & 4 TIM2 (32-bit) TIM1 GPIOs IOPORT HSE LSE LSE T sensor RX, TX, CTS, RTS LPUART1 & 2 TAMP_IN CC, DBCC FRSTX UCPD1 & 2 HDMI-CEC VREFBUF DAC I/F DAC_OUT1 DAC_OUT2 CRC VREF+ SCL, SDA SCL, SDA SMBA, SMBUS I2C1 & 2 I2C3 DBGMCU WWDG PWRCTRL SYSCFG VDDA VDDIO1 Low-voltage detector VDD VDDIO1/VDDIO2 IRTIM from peripherals PFx Port F Port D PDx PCx Port C PBx Port B PAx Port A Port E PEx NOE, DM, DP USB FS RX, TX FDCAN1 & 2 VDDIO2 VDDIO2 COMP3 Parity HSI16 LSI PLLPCLK RC 16 MHz RC 32 kHz PLL I/F PLLQCLK PLLRCLK DMA DMAMUX Flash memory up to 512 KB SRAM 144 KB RC 48 MHz HSI48 |
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