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STM32G0C1NET3X 数据表(PDF) 139 Page - STMicroelectronics |
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STM32G0C1NET3X 数据表(HTML) 139 Page - STMicroelectronics |
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139 / 159 page  DS13564 Rev 4 139/159 STM32G0C1xC/xE Package information 154 Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below. Figure 51. WLCSP52 package marking example 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. Table 85. WLCSP52 - Recommended PCB design rules Dimension Recommended values Pitch 0.4 mm Dpad 0,225 mm Dsm 0.290 mm typ. (depends on soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm G0C1E6 R Y WW Product identification (1) Date code Revision code Pin 1 identifier |
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