STM32G0C1NET3 datasheet(19/159 Pages) STMICROELECTRONICS

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DS13564 Rev 4

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STM32G0C1xC/xE

Functional overview

3.7.4

Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

•

Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

•

Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the VCORE domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down VCORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

•

Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the VCORE domain. The PLL, as well as the

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