STM32G0C1NET3 datasheet(27/159 Pages) STMICROELECTRONICS

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DS13564 Rev 4

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STM32G0C1xC/xE

Functional overview

Features of the DAC:

•

Two DAC output channels

•

8-bit or 12-bit output mode

•

Buffer offset calibration (factory and user trimming)

•

Left or right data alignment in 12-bit mode

•

Synchronized update capability

•

Noise-wave generation

•

Triangular-wave generation

•

Independent or simultaneous conversion for DAC channels

•

DMA capability for either DAC channel

•

Triggering with timer events, synchronized with DMA

•

Triggering with external events

•

Sample-and-hold low-power mode, with internal or external capacitor

3.16

Voltage reference buffer (VREFBUF)

3.17

Comparators (COMP)

Three embedded rail-to-rail analog comparators have programmable reference voltage

(internal or external), hysteresis, speed (low for low-power) and output polarity.

The reference voltage can be one of the following:

•

external, from an I/O

•

internal, from DAC

•

internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4)

The comparators can wake up the device from Stop mode, generate interrupts, breaks or

triggers for the timers and can be also combined into a window comparator.

3.18

Random-number generator (RNG)

The embedded RNG delivers 32-bit random numbers generated by an integrated analog

circuit.

When enabled, an embedded buffer provides the internal reference voltage to analog

blocks (for example ADC) and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

•

2.048 V

•

2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal

voltage reference buffer is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to

common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

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