Philips Semiconductors

Product Specification Rev.3.0 December 2002

Bumped Wafer Specification

SL2 ICS 20

3

1 SCOPE

This specification describes the electrical, physical

and dimensional properties of Au-bumped sawn

wafers on FFC of I•CODE

1

SLI Label ICs on a

Philips C075EE process and is the base for delivery

of tested I•CODE SLI Label ICs.

2 REFERENCE DOCUMENTS

2.1 Philips Documents

•

MIL-STD 883D Method 3023

•

MIL-STD 883D Method 3015

•

SNW-FQ-627

•

PICTOH-QS007

•

General Specification for 8” Wafer

•

General Quality Specification

•

I•CODE SLI Label IC, Functional Specification

•

Application Note Coil Design Guide

•

Specification of the IBIS Wafermap

3 MECHANICAL SPECIFICATION

3.1 Wafer

•

Diameter:

8”

•

Thickness:

150 µm ± 15 µm

•

Flatness:

max. tbf

3.2 Wafer Backside

•

Material:

Si

•

Treatment:

ground + stress releave

•

Roughness:

Ra max. 0.5 µm

Rt max. 5 µm

3.3 Chip Dimensions

•

Chip size:

900 x 780 µm

•

Scribe lines:

80 / 80 µm

3.4 Passivation

•

Type:

sandwich structure

•

Material:

PSG / Nitride (on top)

•

Thickness:

500 nm / 600 nm

1

I

•CODE is a registered trademark of Philips Electronics N.V.

3.5 Au Bump

•

Bump material:

> 99.9% pure Au

•

Bump hardness:

35 – 80 HV 0.005

•

Bump shear strength:

> 70 MPa

•

Bump height:

18 µm

•

Bump height uniformity:

-

within a die:

± 2 µm

-

within a wafer:

± 3 µm

-

wafer to wafer:

± 4 µm

•

Bump flatness:

± 1.5 µm

•

Bump size:

-

LA, LB

92 x 92 µm

-

VSS

2, TESTIO

62 x 62 µm

•

Pad size (no bump!)

-

LA, LB

78 x 78 µm

-

VSS

3, TESTIO

48 x 48 µm

•

Bump size variation:

± 5 µm

•

Under bump metallisation:

sputtered TiW

4 FAIL-DIE IDENTIFICATION

Every die is electrically tested according to data

sheet.

Identification

of

chips

with

electrical

parameters not conform with the data sheet is done

by inking and wafer mapping (all dies at wafer

periphery are identified as ‘FAIL’).

The ink information refers to unsawn wafers. At

sawn wafers (on FFC) additional ICs are be marked

as ‘FAIL’ in the wafer map if damaged during the

sawing process. These ICs will not be inked.

4.1 Wafer Mapping

Wafer mapping for failed die information is available

on Floppy-Disk.

Format: IBIS format

5 ORDERING INFORMATION

5.1 Bumped die on sawn wafer

•

Order Code:

SL2 ICS20 01DW/V4D

•

12NC:

9352 716 15005

2 VSS is conntected to substrate.

3 VSS is conntected to substrate.