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March 31, 2008

IDT80KSW0004

Datasheet

Signal Definitions

JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in the table below. A functional

overview of the TAP Controller and Boundary Scan registers is provided in the sections following the table.

The system logic TAP controller transitions from state to state, according to the value present on TMS, as sampled on the rising edge of TCK. The

Test-Logic Reset state can be reached either by asserting

TRST or by applying a 1 to TMS for five consecutive cycles of TCK. A state diagram for the

TAP controller appears in Figure 20. The value next to state represent the value that must be applied to TMS on the next rising edge of TCK, to transi-

tion in the direction of the associated arrow.

Figure 20 State Diagram of the CPS-12’s TAP Controller

Pin Name Type

Description

TRST

Input

JTAG RESET

Asynchronous reset for JTAG TAP controller (internal pull-up)

TCK

Input

JTAG Clock

Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge.

JTAG_TDO is output on the falling edge.

TMS

Input

JTAG Mode Select. Requires an external pull-up.

Controls the state transitions for the TAP controller state machine (internal pull-up)

TDI

Input

JTAG Input

Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS

register (internal pull-up)

TDO

Output

JTAG Output

Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP

controller states.

Table 26 JTAG Pin Descriptions

Test- Logic

Reset

Run-Test/

Idle

Select-

DR-Scan

Capture-DR

Shift-DR

Exit1 -DR

Pause-DR

Exit2-DR

Select-

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-DR

Update-IR

11

0

0

0

1

1

0

0

1

1

0

1

0

1

0

0

1

1

1

0

0

11

0

1

0

1

1

0

00

0