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March 31, 2008

IDT80KSW0004

Datasheet

Figure 9 Read Protocol with 10-bit Slave Address (ADS=1)

Figure 10 Write protocol with 7-bit Slave Address (ADS=0).

I2C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must

be provided while the 2 LSB’s associated with word and byte pointers are DON’T CARE and are therefore not transmitted.

Figure 11 Read protocol with 7-bit Slave Address (ADS=0)

CPS-12 configuration and image (Master mode)

There is both a power up master and a command master mode. If powered up in master mode, the CPS-12 polls configuration image from external

memory after the device reset sequence has completed. Once the device has completed its configuration sequence, it will revert to slave mode.

Through a config register write, the device can be commanded to enter master mode, which provides more configuration sequence flexibility. Refer to

“CPS-12 User Manual” for details.

I2C DC Electrical Specifications

Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed during operation. Thus, these pins

must be statically tied to the 1.2V supply or GND.

Tables 9 through 11 below list the SDA and SCL electrical specifications for F/S-mode I2C devices:

Device

Address

[9:8]

11 1 1 0

1 AA

A

A

A

Data

Word #1

MSB Byte

Data

Word #1

Byte #2

Data

Word #1

Byte #3

Data

Word #1

LSB Byte

R/W Bit (R=1, W=0)

817

26

35

44

Data output is from base mem_addr[21:0]

5686 drw05b

Device

Address

[6:0]

0 A

A

AAA

Memory

Address

[21:16]

R/W Bit (R=1, W=0)

817

26

35

44

Memory address loaded is mem_addr[21:0]

XX

A 000

Memory

Address

[15:8]

Memory

Address

[7:0]

0

Data

Word #1

MSB Byte

Incoming data will be written

to mem_addr[21:0]

53

Data

Word #1

Byte #2

R/W Bit (R=1, W=0)

A

26

17

Device

Address

[6:0]

A

A

8

1

A

35

Data

Word #1

MSB Byte

Data

Word #1

Byte #2

Data

Word #1

Byte #3

Data

Word #1

LSB Byte

Data output is from base mem_addr[21:0]