80KSW0004 datasheet(41/48 Pages) RENESAS

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March 31, 2008

IDT80KSW0004

Datasheet

Pin Summary

Name

Function

Supply / Interface

Pin Function Description

ADS

I2C(VDD, GND) / CMOS Input

I2C address width select. Set ADS = GND for 7-bit CPS-12 slave

address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS

REQUIREMENTS ARE UNIQUE FROM THE OTHER I2C PINS.

DNC

Do Not Connect. This pin should be left FLOATING. It should not

be connected to any other signal or power rail.

GND

Digital Ground

(CMOS)

Digital GND. All pins must be tied to single potential power supply

ground plane.

GNDS

Analog Ground

(CMOS)

Analog GND. All pins must be tied to single potential ground sup-

ply plane.

ID0 - ID9

I2C(VDD, GND) / CMOS Input

I2C Slave ID addresses. This should be set statically to Vdd or

GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS

ARE UNQUE FROM THE OTHER I2C PINS.

Not connected

I2C

CMOS Input

Select the I2C Mater or Slave mode. Logic high for Master mode

IRQ

Interrupt

(VDD3, GND) / CMOS Output

This is an interrupt output pin whose value is given by the Error

Management Block.

REF_CLK +/-

SERDES Clock

(VDD, GND) / Differential Input

Differential input clock. This clock is used as the 156.25 MHz ref-

erence for standard SERDES operation.

REXTN,

REXTP

Rext

External bias resistor. Rextn must be connected to Rextp with a

12k Ohm resistor. This establishes the drive bias on the SERDES

output. This provides CML driver stability across process and tem-

perature.

RST

Reset

(VDD3, GND) / CMOS Input

CPS-12 Global Reset. Sets all internal registers to default values.

Resets all PLLs. Resets all port configurations. This is a HARD

Reset.

RX0+/- to

RX11+/-

sRIO Receive

(VDDS, GNDS) / RIO Differential Input

Differential receiver inputs, Lanes 0 to 11

SCL

I2C(VDD3, GND) / CMOS IO

I2C Clock.

SDA

I2C(VDD3, GND) / CMOS IO

I2C Serial Data IO. Data direction is determined by the I2C Read/

Write bit. See I2C section for further detail.

SPD[1:0]

SPD

(VDD, GND) / CMOS Input

Speed Select Pins. These pins define sRIO port speed at RESET

for all ports. The RESET setting may be overridden by subsequent

programming of the QUAD_CTRL register. SPD[1:0] = {00 =

1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins

must remain STATICALLY BIASED before power-up.

TCK

JTAG

(VDD3, GND) / CMOS Input

JTAG Tap Port Clock

TDI

JTAG

(VDD3, GND) / CMOS Input

JTAG Tap Port Input

TDO

JTAG

(VDD3, GND) / CMOS Output

JTAG Tap Port Output

TMS

JTAG

(VDD3, GND) / CMOS Input

JTAG Tap Port Mode Select

TRST

JTAG

(VDD3, GND) / CMOS Input

JTAG Tap Port Asynchronous Reset

TX0+/- to

TX11+/-

sRIO Transmit

(VDDS, GNDS) / RIO Differential Output

Differential transmitter outputs, Lanes 0 to 11

Table 36 Pin Summary (Alphabetical)

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