7

I2C register map

The STWBC86 can be monitored and controlled by accessing the internal registers via I2C interface. The

following registers map reports the accessible addresses. Addresses not shown in the map and blank bits have to

be considered reserved and not altered as well.

Table 5. Register abbreviations

Register type

Description

R/W

can read and write the bits

R

can read only

W

can write only

Table 6. Chip information

Address

Register name

R/W

Default

Description

0x0000

Chip ID Low

R

0x56

Chip ID [7..0]

0x0001

Chip ID High

R

0x00

Chip ID [15..8]

0x0002

Chip revision

R

0x02

Chip revision [7..0]

0x0003

Customer ID

R

0x00

Customer ID [7..0]

0x0004

ROM ID

R

0x18

ROM ID [7..0]

0x0005

ROM ID

R

0x01

ROM ID [15..8]

0x0006

NVM Patch ID

R

-

NVM patch ID [7..0]

0x0007

NVM Patch ID

R

-

NVM patch ID [15..8]

0x000A

Configuration ID

R

-

Configuration ID [7..0]

0x000B

Configuration ID

R

-

Configuration ID [15..8]

0x000C

Production ID

R

0x07

PE ID [7..0]

0x000E

Operation mode

R

0x03

0x1: Standalone (debug) mode ; 0x3: Qi TX mode

0x0010 ..0

x001F

Device ID

R

-

Device ID Bytes 0 ...15

Table 7. System information

Address

Register name

R/W

Default

Description

0x0020

System command

RW

-

Bit 0: Switch to TX command

Write 1 to switch to Qi TX mode

Bit 1..7 Reserved

0x002C

System error

R

-

Bit 0: Core hard fault error

0: No hard fault error detected

1: Hard fault error detected

R

-

Bit 1: HW WDT trigger latch

0: HW WDT not triggered

1: HW WDT triggered

R

-

Bit 2: FTP IP error

0: No FTP IP error detected

STWBC86

I2C register

map

DS14079 - Rev 1

page 15/40