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STWBC86 数据表(PDF) 23 Page - STMicroelectronics |
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STWBC86 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 40 page ![]() Address Register name R/W Default Description 0x00C9 TX interrupt latch Byte 1 1: latch R - Bit5: TX ID PKT RCVD LTCH ID packet received interrupt latch 1: latch R - Bit6: TX CFG PKT RCVD LTCH Configuration packet received interrupt latch 1: latch R - Bit7: TX PP PKT RCVD LTCH PP packet received interrupt latch 1: latch 0x00CA TX interrupt latch Byte 2 R - Bit0: TX BRIDGE MD LTCH Bridge mode (half/full) changed interrupt latch 1: latch R - Bit1: TX FOD DET LTCH TX FOD detect interrupt latch 1: latch R - Bit2: TX PPTC UPDATE LTCH The power transfer contract is successfully updated after negotiation/renegotiation 1: latch R - Bit 3: TX DTS SUCC LTCH DTS Send data stream successfully latch 1: latch R - Bit 4: TX DTS SEND END TO LTCH DTS stopped sending due to time out latch 1: latch R - Bit 5: TX DTS SEND END RST LTCH DTS stopped sending due to reset latch 1: latch R - Bit 6: TX DTS RCVD SUCC LTCH DTS received data successfully latch 1: latch R - Bit7: TX DTS RCVD END TO LTCH DTS stopped receiving due to time out latch 1: latch 0x00CB TX interrupt latch Byte 3 Reserved Table 15. TX Interrupt status Address Register name R/W Default Description 0x00CC TX interrupt status Byte 0 R - Bit 0: TX OVTP STAT Over temperature protection status R - Bit 1: TX OCP STAT STWBC86 I2C register map DS14079 - Rev 1 page 23/40 |
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