8.2

Reference schematic

A typical schematic of STWBC86 in a 5W BPP application is shown below.

8.3

PCB routing guidelines

1.

Auxiliary 1V8 and 5V0 LDO filtering capacitors should be placed as close to the STWBC86 as possible.

Connection traces should be short and placed in top layer. Capacitors connected directly to a GND plane.

2.

Power ground(VSSP) will carry the sum of ripple current from VINV/CINV and DC current from VIN, return

paths from LDO caps should avoid these high currents.

3.

CINV and CIN capacitors should be placed close to STWBC86.

4.

Power traces (AC1, AC2, VINV, VIN) should be kept wide enough to a sustain high current. Duplicating

these traces in inner layers is advisable wherever possible.

5.

AC1 and AC2 tracks should be routed close to each other to minimize the area of the resulting loop.

6.

Communication signals (I2C), Sensing and Input monitoring signals to be routed away from High di/dt

(AC1,AC2)switching signals , to Minimize interference.

7.

Thermal performance and grounding should be always optimized by preserving bottom layer (usually

assigned to ground) integrity.

8.4

External components selection

TX series resonant circuit components

The series capacitance Cser is an essential part of the series resonant circuit, therefore, it should show an

excellent quality factor, relatively high RMS current capability and superior capacitance stability in the frequency

range of interest.

Capacitance tolerance and stability strongly depend on the dielectric type used. COG type capacitors are

recommended for their stable performance across various temperatures and voltage levels.

STWBC86

Reference schematic

DS14079 - Rev 1

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