ERTEC datasheet(32/51 Pages) RENESAS

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Data Sheet A17989EE2V0DS00

µPD800261

Parameter

Symbol

Test

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock frequencyNote 1

PFC

150

MHz

Oscillator clock frequencyNote 2

PLL_FC

- 50 ppm

+ 50 ppm

MHz

Reference clock frequencyNote 3

REF_Clk_FC

- 50 ppm

+ 50 ppm

MHz

Reference clock stability

REF_Clk_TCS

-0.2

0.2

Supply currentNote 4, 5

1.5 V supply

IDD Core

10 Base-TX

mode

450

3.3 V supply

IDD IO

235

Supply currentNote 4, 5

1.5 V supply

IDD Core

100 Base-

TX mode

400

535

3.3 V supply

IDD IO

100

175

Supply currentNote 4, 5

1.5 V supply

IDD Core

100 Base-

FX mode

435

3.3 V supply

IDD IO

Power

consumptionNote 4, 5

1.5 V supply

PDD Core

10 Base-TX

mode

670

3.3 V supply

PDD IO

770

total

PDD

1440

Power

consumptionNote 4, 5

1.5 V supply

PDD Core

100 Base-

TX mode

600

800

3.3 V supply

PDD IO

330

570

total

PDD

990

1370

Power

consumptionNote 4, 5

1.5 V supply

PDD Core

100 Base-

FX mode

650

3.3 V supply

PDD IO

280

total

PDD

930

Notes: 1. The CPU clock is an internal signal. Different CPU core operation frequencies can be selected via

hardware settings during reset; possible settings are 50/100/150 MHz.

2. The oscillator clock is present at the CLKP_A and CLKP_B pins.

3. The reference clock is available at the REF_CLK pin, if the CONFIG1 pin was pulled low during the

active reset phase.

4. Typical values for supply currents and power consumption have been measured under the following

conditions:

•

Nominal operating voltages and temperature (VDD IO = 3.3 V, VDD Core = 1.5 V, TA = 25°C

•

Operation of ERTEC 200 on the EB200 evaluation board with 150 MHz core clock frequency

•

SDRAM test program and Ethernet traffic running; internal PHYs set to 100 Base-TX mode

•

No activity on LBU interface

5. Maximum values for supply currents and power consumption have been calculated for

VDD IO = 3.6 V and VDD Core = 1.65 V at TA = 85°C.

Table 2-2:

Recommended Operating Conditions (2/2)

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