P9225-R Datasheet

© 2018 Integrated Device Technology, Inc.

16

November 12, 2018

8. Theory of Operation

The P9225-R is a highly-integrated, wireless power receiver targeted for 5W applications supporting both WPC and PMA standards. The device

integrates a full-wave synchronous rectifier, low-dropout (LDO) linear regulator, and a 32-bit ARM®-based M0 processor to manage all of the

digital control required to comply with the WPC-1.2.4 and PMA communication protocols. Using the near-field inductive power transfer, the

receiver converts the AC signal to DC voltage using the integrated synchronous rectifier. The capacitor connected to the output of the rectifier

smooths the full-wave rectified voltage into a DC voltage. After the internal biasing circuit is enabled, the “Synchronous Rectifier Control” block

operates the switches of the rectifier in various modes to maintain reliable connections and optimal efficiency.

The rectifier voltage and the output current are sampled periodically and digitized by the analog-to-digital converter (ADC). The digital

equivalents of the voltage and current are supplied to the internal control logic, which determines whether the loading conditions on the VRECT

pin indicate that a change in the operating point is required. If the load is heavy enough and brings the voltage at VRECT below its target, the

transmitter is instructed to increase the transmit power. If the voltage at VRECT is higher than its target, the transmitter is instructed to lower

the transmit power. The P9225-R will modulate the load or coil voltage to send the instructions to the transmitter in WPC Mode. To maximize

efficiency, the voltage at VRECT is programmed to decrease as the LDO’s load current increases. The internal temperature is continuously

monitored to ensure proper operation.

In the event that the VRECT voltage increases above 12V, Control Error Packets will be sent to the transmitter in an attempt to bring the rectifier

voltage back to a safe operating voltage level while simultaneously clamping the incoming energy using the open-drain SINK pin for VRECT

linear clamping. The clamp is released when the VRECT voltage falls below VOVP-DC minus VOVP-HYS (see Table 5).

The receiver utilizes IDT’s proprietary voltage clamping scheme, which limits the maximum voltage at the rectifier pin to 12V, reducing the

voltage rating on the output capacitors while eliminating the need for over-voltage protection (OVP) capacitors. As a result, it provides a small

application area, making it an industry-leading wireless power receiver for high power density applications. Combined with the P9038-R

transmitter, the P9225-R is a complete wireless power system solution.

8.1 LDO – Low Dropout Regulators

The P9225-R has three low-dropout linear regulators. The main regulator provides the power required by the battery charger, and the output

voltage can be set in the range of 4.5V to 5.5V. For more information about setting the output voltage, see section 8.2. It is important to connect

a 22µF ceramic capacitance to the OUT pin.

The other two regulators, VDD5V and VDD18, bias the internal circuitry of the receiver. These LDOs must have local 1µF ceramic capacitors

placed as close as possible to the pins.

8.2 Setting the Output Voltage – VOSET

The output voltage on the P9225-R is programmed by connecting the center tap of the external resistors R34 and R33 to the VOSET pin as

shown in the application schematic in Figure 22.

The default output voltage is set to 5V in the P9225-R Evaluation Board provided in the P9225-R Evaluation Kit. Table 6 shows the resistor

combination values for the target output voltage settings.

Table 6.

Setting the Output Voltage

R34

R33

Output Voltage

10kΩ

OPEN

4.5V

10kΩ

49.9kΩ

4.6V

10kΩ

34kΩ

4.7V

10kΩ

20kΩ

4.8V

10kΩ

14.7kΩ

4.9V

OPEN

10kΩ

5.0V