P9242-R Datasheet

© 2018 Integrated Device Technology, Inc

3

January 16, 2018

11.2 Recommended Coils .........................................................................................................................................................................29

11.3 Typical Application Schematic...........................................................................................................................................................30

11.4 Bill of Materials (BOM).......................................................................................................................................................................31

12. Package Outline Drawings .........................................................................................................................................................................34

13. Special Notes: NDG 48-VFQFN Package Assembly..................................................................................................................................34

14. Marking Diagram ........................................................................................................................................................................................34

15. Ordering Information...................................................................................................................................................................................34

16. Revision History..........................................................................................................................................................................................35

List of Figures

Figure 1. Pin Assignments..................................................................................................................................................................................5

Figure 2. Efficiency vs. Output Load: VOUT_RX = 12V.........................................................................................................................................11

Figure 3. Efficiency vs. Output Load: VOUT_RX = 9V...........................................................................................................................................11

Figure 4. Efficiency vs. Output Load: VOUT_RX = 5V...........................................................................................................................................11

Figure 5. Load Regulation vs. Output Load: VCC_5V in Schematic Figure 25 ................................................................................................11

Figure 6. Load Regulation vs. Output Load: LDO33.........................................................................................................................................11

Figure 7. Load Regulation vs. Output Load: LDO18.........................................................................................................................................11

Figure 8. Over-Current Limit vs. VILIM ...............................................................................................................................................................12

Figure 9. Voltage and Current Signal for Demodulation ...................................................................................................................................12

Figure 10. Enable Startup...................................................................................................................................................................................12

Figure 11. Communication Packet during RX Load Step from 0 to 1.3A............................................................................................................12

Figure 12. Communication Packet during RX Load Step from 1.3A to 0............................................................................................................12

Figure 13. Functional Block Diagram..................................................................................................................................................................13

Figure 14. Voltage Mode Envelope Detector......................................................................................................................................................16

Figure 15. Current Mode Envelope Detector ......................................................................................................................................................16

Figure 16. NTC Thermistor Connection to TS Pin ..............................................................................................................................................17

Figure 17. UVLO Threshold Definition................................................................................................................................................................19

Figure 18. Example of Differential Bi-phase Encoding for FSK ..........................................................................................................................21

Figure 19. Example of Asynchronous Serial Byte Format for FSK.....................................................................................................................21

Figure 20. Bit Decoding Scheme ........................................................................................................................................................................22

Figure 21. Byte Decoding Scheme .....................................................................................................................................................................22

Figure 22. Communication Packet Structure ......................................................................................................................................................22

Figure 23. WPC Power Transfer Phases Flow Chart .........................................................................................................................................23

Figure 24. I2C Access Read Protocol and Write Protocol ..................................................................................................................................25

Figure 25. P9242-R Typical Application Schematic V2.3 ...................................................................................................................................30