P9242-R Datasheet

© 2018 Integrated Device Technology, Inc

26

January 16, 2018

From Master

From Slave

ACK

ACK

ACK

DataByte_1

A

A

DataByte_3

A

818181

ACK

DataByte_0

A

81

Clocks

. . . .

DataByte_2

Write Protocol

P

ACK

ACK

CmdByte_1

A

A

CmdFlag_1

818181

ACK

CmdByte_0

A

81

Clocks

CmdFlag_0

A/A

1

NAK

Start

61HEX

ACK

06HEX

ACK

80HEX

ACK

R/W

S

Slave Address

A

Memory Address

MSB

0

A

Memory Address

LSB

A

. . . .

17

18181

1

Clocks

LSB = Least Significant Byte

MSB = Most Significant Byte

A = Acknowledge (SDA LOW)

A = Not Acknowledge (SDA HIGH)

S = Start Condition

Sr = Restart Condition

P = Stop Condition

10.2 Register Addresses and Definitions

The tables in this section provide a comprehensive list of address locations, field names, available operations (R or RW), default values, and

functional descriptions of all internally accessible registers contained within the P9242-R. The default I2 C slave address is 61HEX. The address

of each register has a two-byte structure. For example, the address of the device ID high byte is 01HEX and 05HEX.

Table 10. Device ID Register

Address and Bit

Register Field Name

R/W

Default

Function and Description

0104HEX [7:0]

Device_ID_L

R

42HEX

Device ID low byte

0105HEX [7:0]

Device_ID_H

R

92HEX

Device ID high byte

Table 11. Firmware Major Revision

Address and Bit

Register Field Name

R/W

Default

Function and Description

010CHEX [7:0]

FW_Major_Rev_L

R

06HEX

Major firmware revision low byte

010DHEX [7:0]

FW_Major_Rev_H

R

00HEX

Major firmware revision high byte