Data Sheet

ADL8112

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 9 of 27

Figure 3. Pin Configuration

Table 11. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD1

Drain Bias Voltage. See Figure 5 for the interface schematic.

2

RBIAS

Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external

resistor. See Figure 10 for the interface schematic.

3, 5, 8, 10 to 12, 14, 17, 19 to 22, 24 to

26, 28

GND

RF and DC Ground. See Figure 4 for the interface schematic.

4

RFIN

RF Input. This pin is DC-coupled and matched to 50 Ω. A DC blocking capacitor is required if the RF

line potential is not equal to 0 V DC. See Figure 11 for the interface schematic.

6, 7

VA , VB

Control Input. See Figure 8 and Figure 9 for the interface schematics.

9, 13

OUT_B, IN_B

External Bypass Path B. These pins are DC-coupled and matched to 50 Ω. A DC blocking capacitor is

required if the RF line potential is not equal to 0 V DC. See Figure 11 for the interface schematic.

15

VSS2

Negative Bias Voltage for the Switch.

16

VDD2

Positive Bias Voltage for the Switch.

18

RFOUT

RF Output. This pin is DC-coupled and matched to 50 Ω. A DC blocking capacitor is required if the RF

line potential is not equal to 0 V DC. See Figure 11 for the interface schematic

23, 27

IN_A, OUT_A

External Bypass Path A. These pins are DC-coupled and matched to 50 Ω. A DC blocking capacitor is

required if the RF line potential is not equal to 0 V DC. See Figure 11 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and DC ground.

INTERFACE SCHEMATICS

Figure 4. GND Interface Schematic

Figure 5. VDD1 Interface Schematic

Figure 6. VDD2 Interface Schematic

Figure 7. VSS2 Interface Schematic

Figure 8. VA Interface Schematic

Figure 9. VB Interface Schematic