ADL8112ACCZ-R7 datasheet(24/27 Pages) AD

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Data Sheet

ADL8112

APPLICATIONS INFORMATION

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Rev. 0 | 24 of 27

The basic connections for operating the ADL8112 are shown in Fig-

ure 83. No additional external power supply decoupling capacitors

are required. An 8.5 V DC bias is supplied to the amplifier via the

VDD1 pin. The bias current of the amplifier is set by a resistor

connected between the RBIAS pin and VDD1. Table 13 depicts the

IDQ vs. various RBIAS values for the VDD1 voltage of 8.5 V. Do not

leave the RBIAS pin open.

Table 13. Recommended Bias Resistor Values at VDD1 = 8.5 V

RBIAS (Ω)

IDQ (mA)

IDQ_AMP (mA)

IRBIAS (mA)

168

100

332

554

908

1455

Power for the two SP4T switches comes from the +3.3 V and −3.3

V applied to the VDD2 and VSS2 pins, respectively.

VA and VB are digital inputs that set the operating modes shown in

Table 12. The high logic state is between 1.2 V and 3.3 V and the

low logic state is 0.8 V to 0 V.

Figure 82 shows the time domain response at RFOUT to the

switching voltages on VA and VB when RFIN is driven by a steady

level of approximately 2.5 dBm at 250 MHz.

Both of the external bypass connection paths (External Bypass

A and External Bypass B) are left open. When VA and VB are

low, the ADL8112 is in internal amplifier mode. With VA and VB

high, the device switches to internal bypass mode, and the output

drops correspondingly. When VA and VB are low or high, the

device switches to either External Bypass A or External Bypass

B. Because these two paths are left open in this case, no signal

appears at the output for both cases.

Figure 82. Time Domain Response of RFOUT to Switching of VA and VB

Voltages with a Continuous 2.5 dBm RF Input

Figure 83. Basic Connections and Evaluation Board Schematic

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