| 数据搜索系统,热门电子元器件搜索 |
|
AD9411/PCB 数据表(PDF) 5 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9411/PCB 数据表(HTML) 5 Page - Analog Devices |
|
5 / 28 page ![]() AD9411 Rev. A | Page 5 of 28 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 3. AD9411-170 AD9411-200 Parameter Temp Test Level Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK–)1 Differential Input Voltage2 Full IV 0.2 0.2 V Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ Input Capacitance 25°C V 4 4 pF LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Logic 1 Input Current Full VI 190 190 µA Logic 0 Input Current Full VI 10 10 µA Input Resistance 25°C V 30 30 kΩ Input Capacitance 25°C V 4 4 pF LVDS LOGIC OUTPUTS4 VOD Differential Output Voltage Full VI 247 454 247 454 mV VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V Output Coding Twos Complement or Binary Twos Complement or Binary 1 See the section. Equivalent Circuits 2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV. 3 Clock inputs’ common mode can be externally set, such that 0.9 V < CLK ± < 2.6 V. 4 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance). |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |