AD9411SLASHPCB datasheet(19/28 Pages) AD

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AD9411

Rev. A | Page 19 of 28

S5 = AVDD

VIN+

2.8V

768mV

2.8V

VIN– = 2.8V

Figure 41. Single-Ended Analog Input Range

ANALOG INPUT COMMON MODE (V)

3.2

2.0

2.2

2.4

2.6

2.8

3.0

SINAD

Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,

(Ain = −.5 dBfs Differential Drive, S5 = 0)

LVDS OUTPUTS

The off-chip drivers provide LVDS compatible output levels. A

3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground

sets the LVDS output current. The RSET resistor current is

ratioed on-chip, setting the output current at each output equal

to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termi-

nation resistor placed at the LVDS receiver inputs results in a

nominal 350 mV swing at the receiver. LVDS mode facilitates

interfacing with LVDS receivers in custom ASICs and FPGAs

that have LVDS capability for superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a 100 Ω termination resistor as close to

the receiver as possible. It is recommended to keep the trace

lengths < 4 inches and to keep differential output trace lengths

as equal as possible.

CLOCK OUTPUTS (DCO+, DCO–)

The input clock is buffered on-chip and available off-chip at

DCO+ and DCO–. These clocks can facilitate latching off-chip,

providing a low skew clocking solution (see Figure 2). The on-

chip clock buffers should not drive more than 5 pF of capacitance

to limit switching transient effects on performance. The output

clocks are LVDS signals requiring 100 Ω differential termination

at receiver.

VOLTAGE REFERENCE

A stable and accurate 1.23 V voltage reference is built into the

AD9411 (VREF). The analog input full-scale range is linearly

proportional to the voltage at VREF. Note that an external

reference can be used by connecting the SENSE pin to VDD

(disabling internal reference) and driving VREF with the

external reference source. No appreciable degradation in

performance occurs when VREF is adjusted ±5%. A 0.1 µF

capacitor to ground is recommended at the VREF pin in

internal and external reference applications. Float the SENSE

pin for internal reference operation.

VREF

DISABLE

SENSE

VDD

200

Ω

3.3V

EXTERNAL 1.23V

REFERENCE

0.1

µF

FULL

SCALE

S5 = 0

K = 1.24

S5 = 1

K = 0.62

Ω

Figure 43. Using an External Reference

NOISE POWER RATIO TESTING (NPR)

NPR is a test that is commonly used to characterize the return

path of cable systems where the signals are typically QAM sig-

nals with a “noise-like” frequency spectrum. NPR performance

of the AD9411 was characterized in the lab yielding an effective

NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a

theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB

backoff. The rms noise power of the signal inside the notch is

compared with the rms noise level outside the notch using an

FFT. This test requires sufficiently long record lengths to

guarantee a large number of samples inside the notch. A high-

order band-stop filter that provides the required notch depth

for testing is also needed.

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