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AD9411/PCB 数据表(PDF) 6 Page - Analog Devices |
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AD9411/PCB 数据表(HTML) 6 Page - Analog Devices |
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6 / 28 page ![]() AD9411 Rev. A | Page 6 of 28 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 4. AD9411-170 AD9411-200 Parameter (Conditions) Temp Test Level Min Typ Max Min Typ Max Unit Maximum Conversion Rate1 Full VI 170 200 MSPS Minimum Conversion Rate 1 Full V 40 40 MSPS CLK+ Pulse Width High (tEH) 1 Full IV 2 12.5 2 12.5 ns CLK+ Pulse Width Low (tEL) 1 Full IV 2 12.5 2 12.5 ns OUTPUT (LVDS Mode) Valid Time (tV) Full VI 2.0 2.0 ns Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns DCO Propagation Delay (tCPD) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns Data to DCO Skew (tPD–tCPD) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns Latency Full IV 14 14 Cycles Aperture Delay (tA) 25°C V 1.2 1.2 ns Aperture Uncertainty (Jitter, tJ) 25°C V 0.25 0.25 ps rms Out-of-Range Recovery Time 25°C V 1 1 Cycles 1 All ac specifications tested by driving CLK+ and CLK– differentially. EXPLANATION OF TEST LEVELS I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. CLK+ AIN tEH tEL tPD tCPD 1/fS DCO+ DCO– N–1 N–14 N–13 N 14 CYCLES N+1 N+1 N CLK– DATA OUT Figure 2. LVDS Timing Diagram |
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