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LP3972 数据表(PDF) 21 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
部件名 LP3972
功能描述  Power Management Unit for Advanced Application Processors
PDF  59 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

LP3972 数据表(HTML) 21 Page - National Semiconductor (TI)

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I
2C Compatible Interface
I
2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20207614
I
2C START and STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I
2C master always
generates START and STOP bits. The I
2C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I
2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20207615
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte of data has to be followed by an
acknowledge bit. The acknowledge related clock pulse is
generated by the master. The transmitter releases the SDA
line (HIGH) during the acknowledge clock pulse. The re-
ceiver must pull down the SDA line during the 9th clock
pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte
has been received.
After the START condition, a chip address is sent by the I
2C
master. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3972 address
is 34h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
I
2C CHIP ADDRESS - 7h’34
MSB
ADR6
Bit7
ADR5
Bit6
ADR4
Bit5
ADR3
Bit4
ADR2
Bit3
ADR1
Bit2
ADR0
Bit1
R/W
Bit0
0110100
R/W
www.national.com
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