LP3972 datasheet(6/59 Pages) NSC

6 / 59 page

Pin Descriptions

Pin #

Name

I/O

Type

Description

PWR_ON

CPU Wakeup input, this can be a push button event to indicate the

device has been turned on. Phone / PDA main power button. Signal

is debounced internally on the PMIC.

If the POWER_ON is held low this will indicate to the PMIC to turn

off. Active high Polarity

nTEST_JIG

This is a input signal used for a turn on event coming from the bed

of nails tester during production. Active low polarity.

SPARE

CPU Wakeup input to indicate that a HW external event has

occurred, i.e. flipping the cell phone to power up the display.

EXT_WAKEUP

This signal is asserted when DC POWER source has been

asserted, or when the PWR_ON button is held down to turn off the

PMIC. Wake up on power detection, and power down detection.

FB1

Buck1 input feedback terminal

PWR

Battery Input (Internal circuitry and LDO1-3 power input)

OUT LDO1

PWR

LDO1 output

OUT LDO2

PWR

LDO2 output

nRSTI

Active low Reset pin. Signal used to reset the IC (by default is

pulled high internally). Typically a push button reset.

GND1

Ground

VREF

Bypass Cap. for the high internal impedance reference.

OUT LDO3

PWR

LDO3 output

OUT LDO4

PWR

LDO4 output

IN LDO4

PWR

Power input to LDO4, this can be connected to either from a 1.8V

supply to main Battery supply.

IN BUBATT

PWR

Back Up Battery input supply.

OUT

LDO_RTC

PWR

LDO_RTC output supply to the RTC of the application processor.

nBATT_FLT

Main Battery fault output, indicates the main battery is low

(discharged) or the dc source has been removed from the system.

This gives the processor an indicator that the power will shut down.

During this time the processor will operate from the back up coin

cell.

PGND2

Buck2 NMOS Power Ground

SW2

PWR

Buck2 switcher output

IN Buck2

PWR

Battery input power to Buck2

SDA

I/O

2C Data (Bidirectional)

SCL

2C Clock

FB2

Buck2 input feedback terminal

nRSTO

Reset output from the PMIC to the processor

OUT LDO5

PWR

LDO5 output

IN LDO5

PWR

Power input to LDO5, this can be connected to V

IN or to a separate

1.8V supply.

VDDA

PWR

Analog Power for VREF, BIAS

FB3

Buck3 Feedback

GPIO1 /

nCHG_EN

I/O

General Purpose I/O / Ext. backup battery charger enable pin. This

pin enables the main battery / DC source power to charge the

backup battery. This pin toggled via the application processor. By

grounding this pin the DC source continuously charges the backup

battery

GPIO2

I/O

General Purpose I/O

IN Buck3

PWR

Battery input power to Buck3

LP3972 数据表(PDF) 6 Page - National Semiconductor (TI)

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