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LP3972 数据表(PDF) 7 Page - National Semiconductor (TI) |
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LP3972 数据表(HTML) 7 Page - National Semiconductor (TI) |
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7 / 59 page ![]() Pin Descriptions (Continued) Pin # Name I/O Type Description 32 SW3 O PWR Buck3 switcher output 33 PGND3 G G Buck3 NMOS Power Ground 34 BGND1,2,3 G G Bucks 1, 2 and 3 analog Ground 35 SYNC I D Frequency Synchronization: Connection to an external clock signal PLL to synchronize the PMIC internal oscillator. 36 SYS_EN I D Input Digital enable pin for the high voltage power domain supplies. Output from the Monahans processor. 37 PWR_EN I D Digital enable pin for the Low Voltage domain supplies. Output signal from the Monahans processor 38 PGND1 G G Buck1 NMOS Power Ground 39 SW1 O PWR Buck1 Switcher output 40 VIN Buck1 I PWR Battery input power to Buck1 A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin Note: In this document active low logic items are prefixed with a lowercase “n” www.national.com 7 |
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