LP3972 datasheet(37/59 Pages) NSC

37 / 59 page

2C Compatible Interface (Continued)

NSC DEFINED CONTROL AND STATUS REGISTERS

SYSTEM CONTROL REGISTER 1 (SCR1)

System Control Register 1 (SCR1) 8h’80

Bit

7**

6**

5**

Designation

BPSEN

SENDL

FPWM3

FPWM2

FPWM1

BK_SLOMOD

BK_SSEN

Reset Value

Note: ** denotes one time factory programmable EPROM registers for default values

System Control Register 1 (SCR1) 8h’80 Definitions

Bit

Access

Name

Description

R/W

BPSEN

Bypass System enable safety Lock. Prevents activation of

PWR_EN when SYS_EN is low.

0 = PWR_EN “AND” with SYS_EN signal, Default

1 = PWR_EN independent of SYS_EN

6:5

R/W

SENDL

Delay time for High Voltage Power Domains LDO2, LDO3, LDO4,

Buck2, and Buck3 after activation of SYS_EN. V

CC_LDO1 has no

delay.

Data Code

2h’0

2h’1

2h’2

2h’3

Delay mS

0.0

0.5

1.0

1.4

Notes:

Default

R/W

FPWM3

Buck 3 PWM/PFM Mode select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

R/W

FPWM2

Buck 2 PWM/PFM Mode select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

R/W

FPWM1

Buck 1 PWM/PFM Mode select

0 - Auto Switch between PFM and PWM operation

1 - PWM Mode Only will not switch to PFM

BK_SLOMOD

Buck Spread Spectrum Modulation Buck 1-3

0 = 10 kHz triangular wave spread spectrum modulation

1 = 2 kHz triangular wave spread spectrum modulation

BK_SSEN

Spread spectrum function Buck 1-3

0 = SS Output Disabled

1 = SS Output Enabled

LP3972 数据表(PDF) 37 Page - National Semiconductor (TI)

LP3972 数据表(HTML) 37 Page - National Semiconductor (TI)

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LP3972 数据表(PDF) 37 Page - National Semiconductor (TI)

LP3972 数据表(HTML) 37 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

数据表 下载

链接网址

数据表下载