ADL5385

Rev. 0 | Page 13 of 24

BASIC CONNECTIONS

Figure 27 shows the basic connections for the ADL5385.

R22

10kΩ

VPOS

GND

VPOS

VPOS

SW21

R21

49.9Ω

OFF

ON

LO

VOUT

ENBL

RFPQ

0Ω

RFNQ

0Ω

CFPQ

OPEN

CFNQ

OPEN

QBBP

QBBN

24 VPS3

23 VPS3

22 LOIN

21 LOIP

20 COM3

19 COM3

VOUT 7

VPS1 8

VPS1 9

TEMP 10

VPS2 11

ENBL 12

ADL5385

4 × 4 LFCSP

EXPOSED PADDLE

TEMP

ENB

RTQ

OPEN

R11

0Ω

RFNI

0Ω

RFPI

0Ω

CFNI

OPEN

CFPI

OPEN

IBBN

IBBP

RTI

OPEN

CLOP

0.1µF

CLON

0.1µF

C11

OPEN

C12

0.1µF

R12

0Ω

RTEMP

200Ω

C14

0.1µF

C13

OPEN

C16

0.1µF

C15

OPEN

COUT

0.1µF

R13

0Ω

Figure 27. Basic Connections for the ADL5385

Power Supply and Grounding

All the VPS pins must be connected to the same 5 V source. Adja-

cent pins of the same name can be tied together and decoupled with

a 0.1 μF capacitor. These capacitors are located as close as possible

to the device. The power supply can range from 4.75 V to 5.5 V.

The COM1 pin, COM2 pin, and COM3 pin are tied to the same

ground plane through low impedance paths. The exposed

paddle on the underside of the package is also soldered to a low

thermal and electrical impedance ground plane. If the ground

plane spans multiple layers on the circuit board, they should be

stitched together with nine vias under the exposed paddle. The

Analog Devices AN-772 application note discusses the thermal

and electrical grounding of the LFCSP in greater detail.

Baseband Inputs

The baseband inputs QBBP, QBBN, IBBP, and IBBN must be

driven from a differential source. The nominal drive level of

1.4 V p-p differential (700 mV p-p on each pin) is biased to

a common-mode level of 500 mV dc.

The dc common-mode bias level for the baseband inputs can

range from 400 mV to 600 mV. This results in a reduction in the

usable input ac swing range. The nominal dc bias of 500 mV

allows for the largest ac swing, limited on the bottom end by the

ADL5385 input range and on the top end by the output

compliance range on most Analog Devices DACs.

LO Input

A single-ended LO signal is applied to the LOIP pin through an

ac coupling capacitor. The recommended LO drive power is

−7 dBm. The LO return pin, LOIN, must be ac-coupled to

ground though a low impedance path.

The nominal LO drive of −7 dBm can be increased to up to

+5 dBm. The effect of LO power on sideband suppression and

carrier feedthrough is shown in Figure 15 and Figure 19.

RF Output

The RF output is available at the VOUT pin (Pin 7). This pin

must also be ac-coupled. The VOUT pin has a nominal

broadband impedance of 50 Ω and does not need further

external matching.

OPTIMIZATION

The carrier feedthrough and sideband suppression performance

of the ADL5385 can be improved through the use of optimiza-

tion techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from minute dc offsets that occur

between each of the differential baseband inputs. In an ideal

are equal to zero, and this results in no carrier feedthrough. In

a real modulator, those two quantities are nonzero and, when

mixed with the LO, result in a finite amount of carrier feedthrough.

The ADL5385 is designed to provide a minimal amount of carrier

feedthrough. If even lower carrier feedthrough levels are required,

Q-channel offset is varied until a minimum carrier feedthrough

level is obtained. The Q-channel offset required to achieve this

minimum is held constant while the offset on the I-channel is

adjusted, until a better minimum is reached. Through two

iterations of this process, the carrier feedthrough can be

reduced to as low as the output noise. The ability to null is

sometimes limited by the resolution of the offset adjustment.

Figure 28 shows the relationship of carrier feedthrough vs. dc offset.

–58

–94

VP-VN OFFEST (µV)

–62

–66

–70

–74

–78

–82

–86

–90

Figure 28. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz

Note that throughout the nulling process, the dc bias for the

baseband inputs remains at 500 mV. When no offset is applied,